公开(公告)号：US20090004777A1

公开(公告)日：2009-01-01

申请号：US12124880

申请日：2008-05-21

申请人： Ravi Kanth Kolan ,  Anthony Sun Yi-Sheng ,  Liu Hao ,  Toh Chin Hock

发明人： Ravi Kanth Kolan ,  Anthony Sun Yi-Sheng ,  Liu Hao ,  Toh Chin Hock

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

摘要： A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.

摘要翻译： 一种制造多个堆叠管芯半导体封装的方法，包括：将第二硅晶片连接到第一硅晶片，其中所述第二硅晶片具有多个开口; 将第三硅晶片附接到所述第二硅晶片，其中所述第三硅晶片具有多个开放通孔，并且所述第二和第三硅晶片的所述开放通孔彼此对准; 蚀刻从对准的开放通孔连接晶片的接合材料; 用导体填充对齐的开放通孔; 在对齐的开放通孔的开口端形成导电凸块; 背面研磨第一个硅晶片; 将堆叠的半导体管芯彼此分离; 将堆叠的半导体管芯的凸起端附接到基板上; 封装堆叠的半导体管芯和衬底; 并分离封装的组件。

公开(公告)号：US07824960B2

公开(公告)日：2010-11-02

申请号：US12124830

申请日：2008-05-21

申请人： Liu Hao ,  Ravi Kanth Kolan

发明人： Liu Hao ,  Ravi Kanth Kolan

IPC分类号： H01L21/00

CPC分类号： H01L24/14 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/10135 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14505 ,  H01L2224/17517 ,  H01L2224/81002 ,  H01L2224/8112 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of manufacturing a plurality of stacked die semiconductor packages, including: placing a phase change material between a top surface of a substrate and a bottom surface of a first die; placing a phase change material between a top surface of the first die and a bottom surface of a second die; wherein the first and second dies have a plurality of conductive protrusions on the bottom surfaces of the dies; wherein the first die has a plurality of conductive vias extending from its conductive protrusions, through the first die, to the top surface of the first die; wherein the conductive vias of said first die are in alignment with the conductive protrusions of the second die; and heating the dies and the substrate to cause the second die to become electrically interconnected to the first die and the first die to become electrically connected to the substrate.

摘要翻译： 一种制造多个堆叠裸片半导体封装的方法，包括：将相变材料放置在基板的顶表面和第一管芯的底表面之间; 将相变材料放置在第一管芯的顶表面和第二管芯的底表面之间; 其中所述第一和第二模具在所述模具的底表面上具有多个导电突起; 其中所述第一管芯具有从其导电突起延伸通过所述第一管芯到所述第一管芯的顶表面的多个导电通孔; 其中所述第一管芯的导电通孔与第二管芯的导电突起对准; 并且对所述管芯和所述基板进行加热，以使所述第二管芯与所述第一管芯和所述第一管芯电连接以与所述基板电连接。

公开(公告)号：US07883938B2

公开(公告)日：2011-02-08

申请号：US12124880

申请日：2008-05-21

申请人： Ravi Kanth Kolan ,  Anthony Sun Yi Sheng ,  Liu Hao ,  Toh Chin Hock

发明人： Ravi Kanth Kolan ,  Anthony Sun Yi Sheng ,  Liu Hao ,  Toh Chin Hock

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

摘要： A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.

摘要翻译： 一种制造多个堆叠管芯半导体封装的方法，包括：将第二硅晶片连接到第一硅晶片，其中所述第二硅晶片具有多个开口; 将第三硅晶片附接到所述第二硅晶片，其中所述第三硅晶片具有多个开放通孔，并且所述第二和第三硅晶片的所述开放通孔彼此对准; 蚀刻从对准的开放通孔连接晶片的接合材料; 用导体填充对齐的开放通孔; 在对齐的开放通孔的开口端形成导电凸块; 背面研磨第一个硅晶片; 将堆叠的半导体管芯彼此分离; 将堆叠的半导体管芯的凸起端附接到基板上; 封装堆叠的半导体管芯和衬底; 并分离封装的组件。

公开(公告)号：US20080293186A1

公开(公告)日：2008-11-27

申请号：US12124830

申请日：2008-05-21

申请人： Liu Hao ,  Ravi Kanth Kolan

发明人： Liu Hao ,  Ravi Kanth Kolan

IPC分类号： H01L21/58

CPC分类号： H01L24/14 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/10135 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14505 ,  H01L2224/17517 ,  H01L2224/81002 ,  H01L2224/8112 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method of manufacturing a plurality of stacked die semiconductor packages, including: placing a phase change material between a top surface of a substrate and a bottom surface of a first die; placing a phase change material between a top surface of the first die and a bottom surface of a second die; wherein the first and second dies have a plurality of conductive protrusions on the bottom surfaces of the dies; wherein the first die has a plurality of conductive vias extending from its conductive protrusions, through the first die, to the top surface of the first die; wherein the conductive vias of said first die are in alignment with the conductive protrusions of the second die; and heating the dies and the substrate to cause the second die to become electrically interconnected to the first die and the first die to become electrically connected to the substrate.

摘要翻译： 一种制造多个堆叠裸片半导体封装的方法，包括：将相变材料放置在基板的顶表面和第一管芯的底表面之间; 将相变材料放置在第一管芯的顶表面和第二管芯的底表面之间; 其中所述第一和第二模具在所述模具的底表面上具有多个导电突起; 其中所述第一管芯具有从其导电突起延伸通过所述第一管芯到所述第一管芯的顶表面的多个导电通孔; 其中所述第一管芯的导电通孔与第二管芯的导电突起对准; 并且对所述管芯和所述基板进行加热，以使所述第二管芯与所述第一管芯和所述第一管芯电连接以与所述基板电连接。

公开(公告)号：US08143719B2

公开(公告)日：2012-03-27

申请号：US12133377

申请日：2008-06-05

申请人： Chin Hock Toh ,  Hao Liu ,  Ravi Kanth Kolan

发明人： Chin Hock Toh ,  Hao Liu ,  Ravi Kanth Kolan

IPC分类号： H01L23/34 ,  H01L23/02 ,  H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L23/40

CPC分类号： H01L23/481 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.

摘要翻译： 公开了一种包括具有第一和第二主表面的基板的管芯。 模具具有至少一个未填充的穿过基底的主表面的通孔。 未填充的通孔用作排气口以释放组装期间产生的压力。

公开(公告)号：US08772921B2

公开(公告)日：2014-07-08

申请号：US13347683

申请日：2012-01-10

申请人： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

发明人： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

IPC分类号： H01L23/02

CPC分类号： H01L21/563 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K3/3478 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/043 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

摘要翻译： 介绍了插件。 插入器包括具有第一和第二表面的插入器基座。 再分配层设置在插入器基座的第一表面上。 插入器具有耦合到再分配层的至少一个插入器焊盘。 它还包括在第二表面上的至少一个中介层接触。 插入器触点通过再分配层电耦合到插入器衬垫。 插入器还包括通过插入器基座的至少一个插入器，用于将插入器触点耦合到再分配层。 插入器通孔包括内插器接触件的回流导电材料。

公开(公告)号：US20100109142A1

公开(公告)日：2010-05-06

申请号：US12604613

申请日：2009-10-23

申请人： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

发明人： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

IPC分类号： H01L23/498 ,  H05K1/11 ,  H05K3/10

CPC分类号： H01L21/563 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K3/3478 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/043 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

摘要翻译： 介绍了插件。 插入器包括具有第一和第二表面的插入器基座。 再分配层设置在插入器基座的第一表面上。 插入器具有耦合到再分配层的至少一个插入器焊盘。 它还包括在第二表面上的至少一个中介层接触。 插入器触点通过再分配层电耦合到插入器衬垫。 插入器还包括通过插入器基座的至少一个插入器，用于将插入器触点耦合到再分配层。 插入器通孔包括内插器接触件的回流导电材料。

公开(公告)号：US08399985B2

公开(公告)日：2013-03-19

申请号：US13244630

申请日：2011-09-25

申请人： Ravi Kanth Kolan ,  Hao Liu ,  Chin Hock Toh

发明人： Ravi Kanth Kolan ,  Hao Liu ,  Chin Hock Toh

IPC分类号： H01L23/36

CPC分类号： H01L25/0657 ,  H01L21/50 ,  H01L23/10 ,  H01L23/24 ,  H01L23/3128 ,  H01L24/81 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/0401

摘要： A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.

摘要翻译： 芯片封装包括具有第一和第二主表面的载体。 第一主表面包括被非活性区域包围的有源区域。 芯片封装包括有源区中的接触焊盘，用于与芯片的芯片触点配合。 支撑结构设置在第一主表面的无活性区域上。 支撑结构形成围绕活动区域的坝。 当芯片或芯片堆叠安装在有源区域中时，坝和芯片或芯片堆叠之间存在间隔。 间距创建了用于散热的常规路径。

公开(公告)号：US08030761B2

公开(公告)日：2011-10-04

申请号：US12125924

申请日：2008-05-23

申请人： Ravi Kanth Kolan ,  Hao Liu ,  Chin Hock Toh

发明人： Ravi Kanth Kolan ,  Hao Liu ,  Chin Hock Toh

IPC分类号： H01L23/36

CPC分类号： H01L25/0657 ,  H01L21/50 ,  H01L23/10 ,  H01L23/24 ,  H01L23/3128 ,  H01L24/81 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/16315 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/0401

摘要： A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.

摘要翻译： 芯片封装包括具有第一和第二主表面的载体。 第一主表面包括被非活性区域包围的有源区域。 芯片封装包括有源区中的接触焊盘，用于与芯片的芯片触点配合。 支撑结构设置在第一主表面的无活性区域上。 支撑结构形成围绕活动区域的坝。 当芯片或芯片堆叠安装在有源区域中时，坝和芯片或芯片堆叠之间存在间隔。 间距创建了用于散热的常规路径。

公开(公告)号：US08586465B2

公开(公告)日：2013-11-19

申请号：US12133376

申请日：2008-06-05

申请人： Hao Liu ,  Yi Sheng Anthony Sun ,  Ravi Kanth Kolan ,  Chin Hock Toh

发明人： Hao Liu ,  Yi Sheng Anthony Sun ,  Ravi Kanth Kolan ,  Chin Hock Toh

IPC分类号： H01L21/768

CPC分类号： H01L24/80 ,  H01L21/768 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.

摘要翻译： 公开了一种用于制造包装用模具的方法。 提供具有第一和第二主表面的模具。 在模具的第一主表面上形成通孔和掩模层。 掩模包括露出通孔的掩模开口。 掩模开口用导电材料填充。 该方法包括回流以至少部分地填充通孔和接触开口，以在掩模开口中的通孔和表面接触中形成通孔接触。