公开(公告)号：US06908841B2

公开(公告)日：2005-06-21

申请号：US10251453

申请日：2002-09-20

申请人： Lloyd G. Burrell ,  Douglas Kemerer ,  Henry A. Nye, III ,  Hans-Joachim Barth ,  Emmanuel F. Crabbe ,  David Anderson ,  Joseph Chan

发明人： Lloyd G. Burrell ,  Douglas Kemerer ,  Henry A. Nye, III ,  Hans-Joachim Barth ,  Emmanuel F. Crabbe ,  David Anderson ,  Joseph Chan

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05546 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor device (200) having support structures (218, 226, 236) beneath wirebond regions (214) of contact pads (204) and a method of forming same. Low modulus dielectric layers (216, 222, 232) are disposed over a workpiece (212). Support structures (218, 226, 236) are formed in the low modulus dielectric layers (216, 222, 232), and support vias (224, 234) are formed between the support structures (218, 226, 236). A high modulus dielectric film (220, 230) is disposed between each low modulus dielectric layer (216, 222, 232), and a high modulus dielectric layer (256) is disposed over the top low modulus dielectric layer (232). Contact pads (204) are formed in the high modulus dielectric layer (256). Each support via (234) within the low modulus dielectric layer (232) resides directly above a support via (224) in the underlying low modulus dielectric layer (222), to form a plurality of via support stacks within the low modulus dielectric layers (216, 222, 232).

摘要翻译： 一种在接触焊盘（204）的引线键合区域（214）下方具有支撑结构（218,226,236）的半导体器件（200）及其形成方法。 低模量介电层（216,222,232）设置在工件（212）上方。 支撑结构（218,226,236）形成在低模量电介质层（216,222,232）中，并且支撑通孔（224,234）形成在支撑结构（218,226,236）之间。 高模量介电膜（220,230）设置在每个低模量介电层（216,222,232）之间，并且高模量介电层（256）设置在顶部低模量介电层（232）之上。 接触焊盘（204）形成在高模量介电层（256）中。 在低模量介电层（232）内的每个支撑件（234）直接位于下面的低模量介电层（222）中的支撑通孔（224）的上方，以在低模量介电层（222）内形成多个通孔支撑堆叠 216,222,232）。

公开(公告)号：US20080086706A1

公开(公告)日：2008-04-10

申请号：US11941342

申请日：2007-11-16

申请人： Corey Barrows ,  Douglas Kemerer ,  Stephen Shuma ,  Douglas Stout ,  Oscar Strohacker ,  Mark Styduhar ,  Paul Zuchowski

发明人： Corey Barrows ,  Douglas Kemerer ,  Stephen Shuma ,  Douglas Stout ,  Oscar Strohacker ,  Mark Styduhar ,  Paul Zuchowski

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  H01L27/088 ,  H01L27/092

摘要： A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.

摘要翻译： 设计结构。 该设计结构包括：具有设计的第一V FET的第一组FET和具有设计的第二V FET的第二组FET，第一V T 与第二V 不同; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，被配置为基于所述第一监视电路和所述第二监视电路的性能测量来产生比较信号; 控制单元，响应于比较信号并被配置为基于比较信号产生控制信号调节器; 以及响应于所述控制信号并被配置为所述第二组FET的FET的电压偏置阱的可调电压调节器，所述电压偏置值基于所述控制信号施加。

公开(公告)号：US20070176295A1

公开(公告)日：2007-08-02

申请号：US11307325

申请日：2006-02-01

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Jason Gill ,  Douglas Kemerer ,  Tom Lee

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Jason Gill ,  Douglas Kemerer ,  Tom Lee

IPC分类号： H01L21/44

CPC分类号： H01L27/0688 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/016 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact via scheme with staggered contact vias to, interalia, increase current density of a resistor by mitigating electromigration and reducing the resistive heating of each contact via is disclosed. The contact via scheme increases the current density of a thin film resistor by increasing the number of current carrying contact vias and by arranging the contact vias in staggered arrangement, which redistributes the current at the ends of the resistor. Hence, the contact via scheme decreases the current density per contact via and enables a higher maximum current density for the resistor. A method and a semiconductor device are also disclosed.

摘要翻译： 公开了一种具有交错通孔的接触通孔方案，通过减轻电迁移并降低每个接触通孔的电阻加热来增加电阻器的电流密度。 接触通孔方案通过增加载流接触通孔的数量并且通过以交错布置布置接触通孔来增加薄膜电阻器的电流密度，其重新分布电阻器末端处的电流。 因此，接触通孔方案降低了每个接触通孔的电流密度，并使得电阻器具有更高的最大电流密度。 还公开了一种方法和半导体器件。

公开(公告)号：US20070162770A1

公开(公告)日：2007-07-12

申请号：US11275535

申请日：2006-01-12

申请人： Corey Barrows ,  Douglas Kemerer ,  Douglas Sinut ,  Peter Twombly

发明人： Corey Barrows ,  Douglas Kemerer ,  Douglas Sinut ,  Peter Twombly

IPC分类号： G05F1/577 ,  G06F1/26

CPC分类号： G06F1/26 ,  Y02P80/14

摘要： Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When the sensing network is selectively connected to the power distribution network at an optimal sensing point, a local voltage feedback signal from that optimal sensing point is generated and used to adjust the power supply voltage and, thus, to manage voltage distribution across the power distribution network. Additionally, the system incorporates a policy for managing the voltage distribution across the power distribution network, a means for profiling voltage drops across the power distribution network and a means for selecting the optimal sensing point based on the policy and the profile. Another embodiment of the system can further control power supply voltages to multiple power distribution networks on the same chip.

摘要翻译： 这里公开了一种用于控制片上配电网络的电源电压的系统。 该系统集成了可编程片上感测网络，可在多个位置选择性地连接到配电网络。 当感测网络在最佳感测点选择性地连接到配电网络时，产生来自该最佳感测点的局部电压反馈信号并用于调整电源电压，并且因此来管理功率分配 网络。 此外，该系统包括用于管理配电网络上的电压分布的策略，用于对配电网络上的压降进行分析的装置以及用于基于策略和配置文件选择最佳感测点的装置。 该系统的另一实施例可以进一步控制同一芯片上的多个配电网络的电源电压。

公开(公告)号：US20050278663A1

公开(公告)日：2005-12-15

申请号：US10709807

申请日：2004-05-28

申请人： Douglas Kemerer ,  Daniel Maynard ,  Gustavo Tellez ,  Lijiang Wang ,  Peter Wissell

发明人： Douglas Kemerer ,  Daniel Maynard ,  Gustavo Tellez ,  Lijiang Wang ,  Peter Wissell

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated circuit for deviations from each design rule; (d) computing a score for each physical design rule, using the corresponding rule scoring equation assigned to each physical design rule, for which one or more deviations were found in step (c); and (e) computing a productivity score for the integrated circuit design based on the scores computed in step (d).

摘要翻译： 一种用于提高集成电路的制造生产率的方法和系统。 该方法包括：（a）生成一组物理设计规则，（b）将规则评分方程分配给所述一组物理设计规则的每个物理设计规则; （c）检查集成电路的物理设计以偏离每个设计规则; （d）使用分配给每个物理设计规则的相应规则评分方程计算每个物理设计规则的分数，在步骤（c）中发现一个或多个偏差; 以及（e）基于步骤（d）中计算出的分数计算集成电路设计的生产率得分。

公开(公告)号：US20050050505A1

公开(公告)日：2005-03-03

申请号：US10604995

申请日：2003-08-29

申请人： Thomas Bednar ,  Timothy Budell ,  Patrick Buffet ,  Alain Caron ,  James Crain ,  Douglas Kemerer ,  Donald Kent ,  Esmaeil Rahmati

发明人： Thomas Bednar ,  Timothy Budell ,  Patrick Buffet ,  Alain Caron ,  James Crain ,  Douglas Kemerer ,  Donald Kent ,  Esmaeil Rahmati

IPC分类号： H01L23/528 ,  G06F17/50 ,  H01L23/52

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip (104) having a contact layer (136) that includes a plurality of Vdd, Vddx, ground and I/O contacts (116, 120, 124, 128) arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. An X-Y power grid (140) is located beneath the contact layer and includes metal layers (LM′) each having a plurality of wires (68) extending in one direction. The direction of the wires alternates from one metal layer to the next adjacent metal layer. A wiring layer (IM) is interposed between the contact layer and power grid layers to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires (144, 148, 152) located alternatingly with one another. The Vddx wires are discontinuous between adjacent quadrants so that the magnitude of Vddx may be different in each quadrant of the chip if desired.

摘要翻译： 一种具有接触层（136）的集成电路芯片（104），该接触层包括多个Vdd，Vddx，接地和I / O触点（116,120,124,128），其以大致径向图案布置，具有对角线和长轴对称 并通常定义四个象限。 X-Y电网（140）位于接触层下方，并且包括金属层（LM'），每个金属层具有沿一个方向延伸的多根电线（68）。 线的方向从一个金属层交替到下一个相邻的金属层。 在接触层和电网层之间插入布线层（IM），以在大致径向的Vdd，Vddx和接地触头与矩形X-Y电网之间提供良好的电气转变。 插入的布线层包括彼此交替布置的Vdd，Vddx和接地线（144,148,152）的同心方形环。 Vddx线在相邻象限之间是不连续的，使得如果需要，Vddx的幅度可以在芯片的每个象限中不同。