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    Defect-free hybrid orientation technology for semiconductor devices
    1.
    发明授权
    Defect-free hybrid orientation technology for semiconductor devices 失效
    半导体器件的无缺陷混合取向技术

    公开(公告)号：US07777306B2

    公开(公告)日：2010-08-17

    申请号：US11682403

    申请日：2007-03-06

    申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

    发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

    IPC分类号： H01L29/04

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78 ,  H01L29/785 ,  Y10T428/12528

    摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

    摘要翻译： 半导体器件包括具有两个晶体取向的半导体材料。 半导体材料形成该器件的有效区域。 在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成 与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

    DEFECT-FREE HYBRID ORIENTATION TECHNOLOGY FOR SEMICONDUCTOR DEVICES
    2.
    发明申请
    DEFECT-FREE HYBRID ORIENTATION TECHNOLOGY FOR SEMICONDUCTOR DEVICES 失效
    用于半导体器件的无缺陷混合方向技术

    公开(公告)号：US20090305472A1

    公开(公告)日：2009-12-10

    申请号：US12543630

    申请日：2009-08-19

    申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

    发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

    IPC分类号： H01L21/762

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78 ,  H01L29/785 ,  Y10T428/12528

    摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

    摘要翻译： 半导体器件包括具有两个晶体取向的半导体材料。 半导体材料形成该器件的有效区域。 在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成 与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

    DEFECT-FREE HYBRID ORIENTATION TECHNOLOGY FOR SEMICONDUCTOR DEVICES
    4.
    发明申请
    DEFECT-FREE HYBRID ORIENTATION TECHNOLOGY FOR SEMICONDUCTOR DEVICES 失效
    用于半导体器件的无缺陷混合方向技术

    公开(公告)号：US20080220280A1

    公开(公告)日：2008-09-11

    申请号：US11682403

    申请日：2007-03-06

    申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

    发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

    IPC分类号： B05D5/12 ,  H01L29/12

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78 ,  H01L29/785 ,  Y10T428/12528

    摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

    摘要翻译： 半导体器件包括具有两个晶体取向的半导体材料。 半导体材料形成该器件的有效区域。 在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成 与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

    Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof
    5.
    发明授权
    Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof 有权
    具有混合体厚度的FET的集成电路芯片及其制造方法

    公开(公告)号：US07968944B2

    公开(公告)日：2011-06-28

    申请号：US12541641

    申请日：2009-08-14

    申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

    发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

    IPC分类号： H01L27/12 ,  H01L29/00

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

    摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

    摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

    Fuse/anti-fuse structure and methods of making and programming same
    6.
    发明授权
    Fuse/anti-fuse structure and methods of making and programming same 有权
    保险丝/反熔丝结构及制作和编程方法相同

    公开(公告)号：US07911025B2

    公开(公告)日：2011-03-22

    申请号：US12127080

    申请日：2008-05-27

    申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

    发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

    摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。 还提供了制造和编程保险丝/反熔丝结构的方法。

    CMOS well structure and method of forming the same
    8.
    发明授权
    CMOS well structure and method of forming the same 失效
    CMOS阱结构及其形成方法

    公开(公告)号：US07709365B2

    公开(公告)日：2010-05-04

    申请号：US11551959

    申请日：2006-10-23

    申请人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

    发明人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

    IPC分类号： H01L21/22 ,  H01L21/38

    CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

    摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

    摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

    CMOS well structure and method of forming the same
    10.
    发明授权
    CMOS well structure and method of forming the same 有权
    CMOS阱结构及其形成方法

    公开(公告)号：US07132323B2

    公开(公告)日：2006-11-07

    申请号：US10713447

    申请日：2003-11-14

    申请人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

    发明人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

    摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

    摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。