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公开(公告)号：US06341097B1
公开(公告)日：2002-01-22
申请号：US09764654
申请日：2001-01-17
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A method and system of refreshing a DRAM having a multitude of successive wordlines. The method comprises the step of starting a refresh cycle, and this starting step includes the steps of (I) counting the wordlines one at a time in succession, (ii) refreshing the wordlines counted over a first period t1, and (iii) at the end of period t1, stopping the refreshing of the wordlines, and continuing the counting of the wordlines for a period t2. The method further comprises the step of, after period t2, restarting the refresh cycle. Preferably, the restarting step includes the steps of, at the end of period t2, delaying for a period t3; and restarting the refresh cycle at the end of period t3. The method may include the further step of adjusting the length of the period t1, and preferably, during the combined periods t1 and t2, all of the wordlines are counted. Also, preferably the processing unit determines the memory space to be refreshed; and, more specifically, this may be accomplished by the processing unit issuing a reset signal to terminate the refresh period t1.
摘要翻译： 一种刷新具有多个连续字线的DRAM的方法和系统。 该方法包括开始刷新周期的步骤，该开始步骤包括以下步骤：（I）一次一个地对一个字线进行计数，（ii）刷新在第一周期t1计数的字线，以及（iii） 时段t1的结束，停止字线的刷新，并且继续对字线计数一段时间t2。 该方法还包括在时段t2之后重新启动刷新周期的步骤。 优选地，重新开始步骤包括以下步骤：在周期t2结束时，延迟时段t3; 并在周期t3结束时重新启动刷新周期。 该方法可以包括调整周期t1的长度的进一步的步骤，优选地，在组合时段t1和t2期间，对所有字线进行计数。 此外，优选地，处理单元确定要刷新的存储器空间; 并且更具体地，这可以由处理单元发出复位信号来终止刷新周期t1来实现。
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公开(公告)号：US06774463B1
公开(公告)日：2004-08-10
申请号：US07842722
申请日：1992-02-24
申请人： Praveen Chaudhari , Richard Joseph Gambino , Eti Ganin , Roger Hilsen Koch , Lia Krusin-Elbaum , Robert Benjamin Laibowitz , George Anthony Sai-Halasz , Yuan-Chen Sun , Matthew Robert Wordeman
发明人： Praveen Chaudhari , Richard Joseph Gambino , Eti Ganin , Roger Hilsen Koch , Lia Krusin-Elbaum , Robert Benjamin Laibowitz , George Anthony Sai-Halasz , Yuan-Chen Sun , Matthew Robert Wordeman
IPC分类号： H01L3900
CPC分类号： H01L29/4966 , H01L29/437 , Y10S505/873
摘要： In a Field Effect Transistor (FET) with a semiconductor channel the use of a high Tc oxide superconductor material in the gate electrode provides both control of parasitic resistance and capacitance and a proper work function when operated at a temperature below the Tc. The 1-2-3 compound oxide superconductors with the general formula Y1Ba2Cu3O7-y where y is approximately 0.1 have the ability in use in FET's to provide convenient work functions, low resistance and capacitance, and to withstand temperatures encountered in processing as the FET is being manufactured.
摘要翻译： 在具有半导体通道的场效应晶体管（FET）中，栅电极中使用高Tc氧化物超导体材料在低于Tc的温度下工作时，提供寄生电阻和电容的控制以及适当的功函数。 具有通式Y1Ba2Cu3O7-y的1-2-3复合氧化物超导体，其中y约为0.1具有在FET中使用的能力，以提供方便的工作功能，低电阻和电容，并且能够承受处理中遇到的温度，因为FET为 被制造。
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公开(公告)号：US06204532B1
公开(公告)日：2001-03-20
申请号：US09412866
申请日：1999-10-05
IPC分类号： H01L2976
CPC分类号： H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： According to the present invention, a method for fabricating vertical circuit devices which include a body contact is disclosed. During the fabrication process, the body of a transistor is formed from a pillar of single crystal silicon. The silicon pillar is formed over a butted junction of N+ and P+ diffusions. This fabrication process results in a pillar structure which has an n+ diffusion contacting a portion of the base of the transistor body and a P+ diffusion contacting the remainder of the base of the transistor body. The proportion of N+ and P+ area at the base of the silicon pillar depends on the overlay of the opening to the butted junction. Gate oxide is grown over the entire pillar and a polysilicon gate material is then deposited and etched to form the transistor gate. Metal contact studs are formed, preferably via deposition. After fabrication, the entire surface of the device can be planarized by using any standard Chemical Mechanical Planarization (CMP) process.
摘要翻译： 根据本发明，公开了一种制造包括身体接触的垂直电路装置的方法。 在制造过程中，晶体管的主体由单晶硅的支柱构成。 硅柱形成在N +和P +扩散的对接结上。 该制造工艺导致柱结构，其具有与晶体管体的基极的一部分接触的n +扩散和接触晶体管体的基极的其余部分的P +扩散。 硅柱底部的N +和P +面积的比例取决于开口对接接头的覆盖面。 栅极氧化物在整个柱上生长，然后沉积并蚀刻多晶硅栅极材料以形成晶体管栅极。 优选通过沉积形成金属接触柱。 在制造之后，通过使用任何标准化学机械平面化（CMP）工艺，可以使器件的整个表面平坦化。
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公开(公告)号：US6020239A
公开(公告)日：2000-02-01
申请号：US14960
申请日：1998-01-28
IPC分类号： H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： According to the present invention, a method for fabricating vertical circuit devices which include a body contact is disclosed. During the fabrication process, the body of a transistor is formed from a pillar of single crystal silicon. The silicon pillar is formed over a butted junction of N+ and P+ diffusions. This fabrication process results in a pillar structure which has an n+ diffusion contacting a portion of the base of the transistor body and a P+ diffusion contacting the remainder of the base of the transistor body. The proportion of N+ and P+ area at the base of the silicon pillar depends on the overlay of the opening to the butted junction. Gate oxide is grown over the entire pillar and a polysilicon gate material is then deposited and etched to form the transistor gate. Metal contact studs are formed, preferably via deposition. After fabrication, the entire surface of the device can be planarized by using any standard Chemical Mechanical Planarization (CMP) process.
摘要翻译： 根据本发明，公开了一种制造包括身体接触的垂直电路装置的方法。 在制造过程中，晶体管的主体由单晶硅的支柱构成。 硅柱形成在N +和P +扩散的对接结上。 该制造工艺导致柱结构，其具有与晶体管体的基极的一部分接触的n +扩散和接触晶体管体的基极的其余部分的P +扩散。 硅柱底部的N +和P +面积的比例取决于开口对接接头的覆盖面。 栅极氧化物在整个柱上生长，然后沉积并蚀刻多晶硅栅极材料以形成晶体管栅极。 优选通过沉积形成金属接触柱。 在制造之后，通过使用任何标准化学机械平面化（CMP）工艺，可以使器件的整个表面平坦化。
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公开(公告)号：US5930178A
公开(公告)日：1999-07-27
申请号：US971494
申请日：1997-11-17
IPC分类号： G11C7/12 , G11C11/4094 , G11C16/04
CPC分类号： G11C11/4094 , G11C7/12
摘要： A voltage control circuit for maintaining voltage levels on a pair of bitlines at a desirable above ground voltage is disclosed herein. In an exemplary embodiment, a semiconductor storage device includes a plurality of pairs of bitlines; a p-type field effect transistor multiplexer (PMUX) connecting each bitline of the pair to a sense amplifier; and a clamping circuit which prevents voltage levels on the bitlines from dwelling below a predetermined minimum voltage level. A method is also disclosed herein in which voltage levels on a pair of bitlines are maintained at a desirable above ground voltage level by connecting each bitline of a pair to a sense amplifier through a p-type field effect transistor multiplexer (PMUX); and clamping each bitline to prevent the voltage level thereon from dwelling below a predetermined minimum voltage level.
摘要翻译： 本文公开了一种用于在期望的地面电压下保持一对位线上的电压电平的电压控制电路。 在示例性实施例中，半导体存储装置包括多对位线; 将该对的每个位线连接到读出放大器的p型场效应晶体管多路复用器（PMUX）; 以及钳位电路，其防止位线上的电压水平低于预定的最小电压电平。 本文还公开了一种方法，其中一对位线上的电压电平通过p型场效应晶体管多路复用器（PMUX）将一对的每个位线连接到读出放大器而保持在理想的接地电压电平; 并夹紧每个位线以防止其上的电压电平低于预定的最小电压电平。
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