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公开(公告)号：US5930178A
公开(公告)日：1999-07-27
申请号：US971494
申请日：1997-11-17
IPC分类号： G11C7/12 , G11C11/4094 , G11C16/04
CPC分类号： G11C11/4094 , G11C7/12
摘要： A voltage control circuit for maintaining voltage levels on a pair of bitlines at a desirable above ground voltage is disclosed herein. In an exemplary embodiment, a semiconductor storage device includes a plurality of pairs of bitlines; a p-type field effect transistor multiplexer (PMUX) connecting each bitline of the pair to a sense amplifier; and a clamping circuit which prevents voltage levels on the bitlines from dwelling below a predetermined minimum voltage level. A method is also disclosed herein in which voltage levels on a pair of bitlines are maintained at a desirable above ground voltage level by connecting each bitline of a pair to a sense amplifier through a p-type field effect transistor multiplexer (PMUX); and clamping each bitline to prevent the voltage level thereon from dwelling below a predetermined minimum voltage level.
摘要翻译： 本文公开了一种用于在期望的地面电压下保持一对位线上的电压电平的电压控制电路。 在示例性实施例中，半导体存储装置包括多对位线; 将该对的每个位线连接到读出放大器的p型场效应晶体管多路复用器（PMUX）; 以及钳位电路，其防止位线上的电压水平低于预定的最小电压电平。 本文还公开了一种方法，其中一对位线上的电压电平通过p型场效应晶体管多路复用器（PMUX）将一对的每个位线连接到读出放大器而保持在理想的接地电压电平; 并夹紧每个位线以防止其上的电压电平低于预定的最小电压电平。
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公开(公告)号：US20120248567A1
公开(公告)日：2012-10-04
申请号：US13494327
申请日：2012-06-12
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.
摘要翻译： 一个结构。 该结构包括：衬底，衬底中的第一电极，衬底和第一电极上的第一电介质层，第一电介质层上方的第二电介质层和埋在第一电介质层中的熔丝元件。 第一电极包括第一导电材料。 第一电介质层的顶表面比第一电介质层的任何其它表面更远离第一电极的顶表面。 第一电介质层包括第一电介质材料和第二电介质材料。 第二电介质层的底表面与第一电介质层的顶表面直接物理接触。 第二电介质层包括第二电介质材料。
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3.发明授权Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering 有权结合了具有减小的结电容和漏极引起的屏障降低的半导体器件结构公开(公告)号：US07984408B2
公开(公告)日：2011-07-19
申请号：US11875013
申请日：2007-10-19
CPC分类号： H01L29/78603 , G11C29/54 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/66636 , H01L29/66772
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。 设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。
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公开(公告)号：US07833873B2
公开(公告)日：2010-11-16
申请号：US12174683
申请日：2008-07-17
IPC分类号： H01L21/76
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.
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5.发明授权Apparatus for implementing enhanced hand shake protocol in microelectronic communication systems 失效用于在微电子通信系统中实现增强的手抖动协议的装置公开(公告)号：US07809340B2
公开(公告)日：2010-10-05
申请号：US12127159
申请日：2008-05-27
IPC分类号： H04B1/04
CPC分类号： H04B1/38
摘要： An apparatus is provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first common 10 mode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, the 15 transmitter terminates communications, drops the common mode level with the idle input being activated.
摘要翻译： 提供了一种用于实现用于微电子通信系统的增强的手抖动协议的装置。 发射机和接收机通过传输链路耦合在一起。 发射机接收空闲输入。 当发射机不发送数据并且发射机向接收单元施加第一公共10模式电平时，空闲输入被激活。 当发射机准备好传输数据并且发射机将共模电平提升到接收单元时，空闲输入被去激活。 响应于接收机检测共模水平上移，接收器接收发送的数据信号。 在发送所需数据之后，15个发射机终止通信，在空闲输入被激活时降低共模电平。
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6.发明授权Design structures incorporating interconnect structures with liner repair layers 有权设计结构包括具有衬里修复层的互连结构公开(公告)号：US07494916B2
公开(公告)日：2009-02-24
申请号：US11875345
申请日：2007-10-19
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76868 , H01L2924/0002 , H01L2924/00
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes an interconnect structure with a liner formed on roughened dielectric material in an insulating layer and a conformal liner repair layer bridging that breaches in the liner. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括互连结构，其具有在绝缘层中的粗糙化介电材料上形成的衬垫和桥接该衬里中的破损的保形衬里修复层。 保形衬里修复层由诸如含钴材料的导电材料形成。 保形衬里修复层可能特别适用于修复布置在与镶嵌互连结构的沟槽和通孔相邻的粗糙化介电材料上的导电衬垫中的不连续性。
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7.发明申请公开(公告)号：US20090007037A1
公开(公告)日：2009-01-01
申请号：US11925413
申请日：2007-10-26
IPC分类号： G06F9/45
CPC分类号： H01L21/28052 , H01L21/28097 , H01L21/823443 , H01L21/82345 , H01L21/823475 , H01L21/823835 , H01L21/823842 , H01L21/823871 , H01L28/20 , H01L29/4933 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers.
摘要翻译： 本发明的实施例一般涉及用于半导体器件的方法，系统和设计结构，更具体地涉及形成部分硅化和完全硅化结构。 制造部分硅化和完全硅化的结构可能涉及创建一个或多个栅极叠层。 可以暴露第一栅极叠层的多晶硅层，并且可以在其上沉积第一金属层以产生部分硅化结构。 此后，可以暴露第二栅极堆叠的多晶硅层，并且可以在其上沉积第二金属层以形成完全硅化的结构。 在一些实施例中，可以不暴露一个或多个栅极叠层的多晶硅层，并且可以用非硅化多晶硅层形成电阻器。
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公开(公告)号：US20090007036A1
公开(公告)日：2009-01-01
申请号：US11925387
申请日：2007-10-26
IPC分类号： G06F9/45
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits.
摘要翻译： 本发明的实施例一般涉及半导体器件的方法，系统和设计结构，更具体地涉及互连半导体器件。 可以在连接一个或多个半导体器件或半导体器件部件的翅片结构的选择性区域上形成硅化物层。 通过提供硅化物翅片结构来局部互连半导体器件，可以避免使用金属触点和金属层，从而形成较小的，较不复杂的电路。
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公开(公告)号：US20080274597A1
公开(公告)日：2008-11-06
申请号：US12174683
申请日：2008-07-17
IPC分类号： H01L21/336
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.
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10.发明申请公开(公告)号：US20080120580A1
公开(公告)日：2008-05-22
申请号：US11875193
申请日：2007-10-19
IPC分类号： G06F17/50
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L21/76885
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure comprises an insulating layer of a dielectric material, an opening having sidewalls extending from a top surface of the insulating layer toward a bottom surface of the insulating layer, and a conductive feature disposed in the opening. The design structure includes a top capping layer disposed on at least a top surface of the conductive feature and a conductive liner layer disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer of the design structure has sidewall portions that project above the top surface of the insulating layer adjacent to the sidewalls of the opening.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括介电材料的绝缘层，具有从绝缘层的顶表面朝向绝缘层的底表面延伸的侧壁的开口以及设置在该开口中的导电特征。 该设计结构包括设置在导电特征的至少顶表面上的顶盖层和至少沿开口的侧壁设置在绝缘层和导电特征之间的导电衬垫层。 该设计结构的导电衬里层具有侧壁部分，该侧壁部分突出在邻近开口侧壁的绝缘层顶表面上方。
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