公开(公告)号：US20130181211A1

公开(公告)日：2013-07-18

申请号：US13353235

申请日：2012-01-18

申请人： Lu-An Chen ,  Chang-Tzu Wang ,  Tai-Hsiang Lai ,  Tien-Hao Tang

发明人： Lu-An Chen ,  Chang-Tzu Wang ,  Tai-Hsiang Lai ,  Tien-Hao Tang

IPC分类号： H01L29/12

CPC分类号： H01L27/0262 ,  H01L29/0692 ,  H01L29/10 ,  H01L29/87

摘要： Provided is a metal oxide semiconductor device, including a substrate, a gate, a first-type first heavily doped region, a first-type drift region, a second-type first heavily doped region, a contact, a first electrode, and a second electrode. The gate is disposed on the substrate. The first-type first heavily doped region is disposed in the substrate at a side of the gate. The first-type drift region is disposed in the substrate at another side of the gate. The second-type first heavily doped region is disposed in the first-type drift region. The contact is electrically connected to the second-type first heavily doped region. The contact is the closest contact to the gate on the first-type drift region. The first electrode is electrically connected to the contact, and the second electrode is electrically connected to the first-type first heavily doped region and the gate.

摘要翻译： 提供了一种金属氧化物半导体器件，其包括衬底，栅极，第一类型的第一重掺杂区域，第一类型漂移区域，第二类型第一重掺杂区域，接触区，第一电极和第二 电极。 栅极设置在基板上。 第一类型的第一重掺杂区域设置在栅极侧的衬底中。 第一类型漂移区域设置在栅极另一侧的衬底中。 第二类型的第一重掺杂区域设置在第一类漂移区域中。 触点电连接到第二类型的第一重掺杂区域。 触点是与第一型漂移区上的栅极最接近的接触点。 第一电极电连接到触点，并且第二电极电连接到第一类型的第一重掺杂区域和栅极。

公开(公告)号：US08716801B2

公开(公告)日：2014-05-06

申请号：US13353235

申请日：2012-01-18

申请人： Lu-An Chen ,  Chang-Tzu Wang ,  Tai-Hsiang Lai ,  Tien-Hao Tang

发明人： Lu-An Chen ,  Chang-Tzu Wang ,  Tai-Hsiang Lai ,  Tien-Hao Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/0262 ,  H01L29/0692 ,  H01L29/10 ,  H01L29/87

摘要： Provided is a metal oxide semiconductor device, including a substrate, a gate, a first-type first heavily doped region, a first-type drift region, a second-type first heavily doped region, a contact, a first electrode, and a second electrode. The gate is disposed on the substrate. The first-type first heavily doped region is disposed in the substrate at a side of the gate. The first-type drift region is disposed in the substrate at another side of the gate. The second-type first heavily doped region is disposed in the first-type drift region. The contact is electrically connected to the second-type first heavily doped region. The contact is the closest contact to the gate on the first-type drift region. The first electrode is electrically connected to the contact, and the second electrode is electrically connected to the first-type first heavily doped region and the gate.

摘要翻译： 提供了一种金属氧化物半导体器件，其包括衬底，栅极，第一类型的第一重掺杂区域，第一类型漂移区域，第二类型第一重掺杂区域，接触区，第一电极和第二 电极。 栅极设置在基板上。 第一类型的第一重掺杂区域设置在栅极侧的衬底中。 第一类漂移区域设置在栅极另一侧的衬底中。 第二类型的第一重掺杂区域设置在第一类漂移区域中。 触点电连接到第二类型的第一重掺杂区域。 触点是与第一型漂移区上的栅极最接近的接触点。 第一电极电连接到触点，并且第二电极电连接到第一类型的第一重掺杂区域和栅极。

公开(公告)号：US08477467B2

公开(公告)日：2013-07-02

申请号：US13190578

申请日：2011-07-26

申请人： Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

发明人： Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

IPC分类号： H02H3/22

CPC分类号： H02H9/046

摘要： An electrostatic discharge protection circuit is located between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first semiconductor switch and a second semiconductor switch. The first semiconductor switch is electrically connected to the first voltage terminal. If a voltage at the first voltage terminal complies with a starting condition, the first semiconductor switch is turned on, so that an electrostatic discharge current flows through the first voltage terminal and the first semiconductor switch. The second semiconductor switch is electrically connected between the first semiconductor switch and the second voltage terminal, wherein the electrostatic discharge current from the first semiconductor switch passes to the second voltage terminal through the second semiconductor switch.

摘要翻译： 静电放电保护电路位于第一电压端子和第二电压端子之间。 静电放电保护电路包括第一半导体开关和第二半导体开关。 第一半导体开关电连接到第一电压端子。 如果第一电压端子处的电压符合启动条件，则第一半导体开关导通，使得静电放电电流流过第一电压端子和第一半导体开关。 第二半导体开关电连接在第一半导体开关和第二电压端子之间，其中来自第一半导体开关的静电放电电流通过第二半导体开关传递到第二电压端子。

公开(公告)号：US20140027856A1

公开(公告)日：2014-01-30

申请号：US13556219

申请日：2012-07-24

申请人： Mei-Ling Chao ,  Yi-Chun Chen ,  Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

发明人： Mei-Ling Chao ,  Yi-Chun Chen ,  Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

IPC分类号： H01L27/06

CPC分类号： H01L27/027 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) includes a semiconductor substrate having the first conductive type, a well having the first conductive type, a buried layer having the second conductive type and a well having the second conductive type. The buried layer having a second conductive type is disposed in the semiconductor substrate under the well having the first conductive type. The well having the second conductive type disposed to divide the well having the first conductive type into a first well and a second well. The well having the second conductive type contacts the buried layer, and the well having the second conductive type and the buried layer are jointly used to isolate the first well from the second well.

摘要翻译： 静电放电（ESD）包括具有第一导电类型的半导体衬底，具有第一导电类型的阱，具有第二导电类型的掩埋层和具有第二导电类型的阱。 具有第二导电类型的掩埋层在具有第一导电类型的阱下面设置在半导体衬底中。 具有第二导电类型的阱被设置成将具有第一导电类型的阱分成第一阱和第二阱。 具有第二导电类型的阱接触掩埋层，并且具有第二导电类型和掩埋层的阱共同用于将第一阱与第二阱隔离。

公开(公告)号：US08530969B2

公开(公告)日：2013-09-10

申请号：US13369423

申请日：2012-02-09

申请人： Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

发明人： Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

IPC分类号： H01L23/62

CPC分类号： H01L29/7835 ,  H01L27/0251

摘要： A semiconductor device includes a substrate, a gate structure, a source structure and a drain structure. The substrate includes a deep well region, and the gate structure is disposed on the deep well region. The source structure is formed within the deep well and located at a first side of the gate structure. The drain structure is formed within the deep well region and located at a second side of the gate structure. The drain structure includes a first doped region of a first conductivity type, a first electrode and a second doped region of a second conductivity type. The first doped region is located in the deep well region; the first electrode is electrically connected to the first doped region. The second doped region is disposed within the first doped region and between the first electrode and the gate structure.

摘要翻译： 半导体器件包括衬底，栅极结构，源极结构和漏极结构。 衬底包括深阱区，并且栅极结构设置在深阱区上。 源结构形成在深阱内并且位于栅极结构的第一侧。 漏极结构形成在深阱区域内，并且位于栅极结构的第二侧。 漏极结构包括第一导电类型的第一掺杂区域，第二导电类型的第一电极和第二掺杂区域。 第一掺杂区位于深井区; 第一电极电连接到第一掺杂区域。 第二掺杂区域设置在第一掺杂区域内并且位于第一电极和栅极结构之间。

公开(公告)号：US08723263B2

公开(公告)日：2014-05-13

申请号：US13556219

申请日：2012-07-24

申请人： Mei-Ling Chao ,  Yi-Chun Chen ,  Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

发明人： Mei-Ling Chao ,  Yi-Chun Chen ,  Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/027 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) includes a semiconductor substrate having the first conductive type, a well having the first conductive type, a buried layer having the second conductive type and a well having the second conductive type. The buried layer having a second conductive type is disposed in the semiconductor substrate under the well having the first conductive type. The well having the second conductive type disposed to divide the well having the first conductive type into a first well and a second well. The well having the second conductive type contacts the buried layer, and the well having the second conductive type and the buried layer are jointly used to isolate the first well from the second well.

摘要翻译： 静电放电（ESD）包括具有第一导电类型的半导体衬底，具有第一导电类型的阱，具有第二导电类型的掩埋层和具有第二导电类型的阱。 具有第二导电类型的掩埋层在具有第一导电类型的阱下面设置在半导体衬底中。 具有第二导电类型的阱被设置成将具有第一导电类型的阱分成第一阱和第二阱。 具有第二导电类型的阱接触掩埋层，并且具有第二导电类型和掩埋层的阱共同用于将第一阱与第二阱隔离。

公开(公告)号：US08507981B2

公开(公告)日：2013-08-13

申请号：US13271239

申请日：2011-10-12

申请人： Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

发明人： Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L29/41758 ,  H01L27/0277 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/7816

摘要： A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source including a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source.

摘要翻译： 一种形成NMOS晶体管的方法包括：形成P基片; 在P基板上形成N阱; 在N阱上形成N漂移区; 在N漂移区上形成n +漏极; 在所述n +漏极上沿纵向方向形成多个第一触点; 在N阱上形成P体; 在所述P体上形成源极，所述源极包括多个n +掺杂区域和沿着所述纵向排列的至少一个p +掺杂区域; 在所述多个n +掺杂区域和所述至少一个p +掺杂区域上形成多个第二接触; 在P体上形成多孔盖; 以及在所述多晶硅栅极和所述源极之间形成栅极氧化物。

公开(公告)号：US20130049112A1

公开(公告)日：2013-02-28

申请号：US13214627

申请日：2011-08-22

申请人： Tai-Hsiang LAI ,  Lu-An Chen ,  Tien-Hao Tang

发明人： Tai-Hsiang LAI ,  Lu-An Chen ,  Tien-Hao Tang

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/0626 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1087 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection device comprises a substrate with a first conductivity, a gate, a drain structure and a source structure. The gate is disposed on a surface of the substrate. The drain structure with a second conductivity type comprises a first doping region with a first doping concentration disposed adjacent to the gate and extending into the substrate from the surface of the substrate, a second doping region extending into and stooped at the first doping region from the surface of the substrate and having a second doping concentration substantially greater than the first doping concentration, and a third doping region disposed in the substrate beneath the second doping region and having a third doping concentration substantially greater than the first doping concentration. The source structure with the second conductivity is disposed in the substrate and adjacent to the gate electrode.

摘要翻译： 静电放电保护器件包括具有第一导电性的衬底，栅极，漏极结构和源极结构。 栅极设置在基板的表面上。 具有第二导电类型的漏极结构包括具有第一掺杂浓度的第一掺杂区，第一掺杂浓度设置为与栅极相邻并且从衬底的表面延伸到衬底中，第二掺杂区延伸到第一掺杂区并从其中弯曲 并且具有基本上大于第一掺杂浓度的第二掺杂浓度，以及设置在第二掺杂区域下方并具有基本上大于第一掺杂浓度的第三掺杂浓度的第三掺杂区域。 具有第二导电性的源结构设置在基板中并与栅电极相邻。

公开(公告)号：US08492834B2

公开(公告)日：2013-07-23

申请号：US13214627

申请日：2011-08-22

申请人： Tai-Hsiang Lai ,  Lu-An Chen ,  Tien-Hao Tang

发明人： Tai-Hsiang Lai ,  Lu-An Chen ,  Tien-Hao Tang

IPC分类号： H01L29/66 ,  H01L23/62

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/0626 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1087 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection device comprises a substrate with a first conductivity, a gate, a drain structure and a source structure. The gate is disposed on a surface of the substrate. The drain structure with a second conductivity type comprises a first doping region with a first doping concentration disposed adjacent to the gate and extending into the substrate from the surface of the substrate, a second doping region extending into and stooped at the first doping region from the surface of the substrate and having a second doping concentration substantially greater than the first doping concentration, and a third doping region disposed in the substrate beneath the second doping region and having a third doping concentration substantially greater than the first doping concentration. The source structure with the second conductivity is disposed in the substrate and adjacent to the gate electrode.

摘要翻译： 静电放电保护器件包括具有第一导电性的衬底，栅极，漏极结构和源极结构。 栅极设置在基板的表面上。 具有第二导电类型的漏极结构包括具有第一掺杂浓度的第一掺杂区，第一掺杂浓度设置为与栅极相邻并且从衬底的表面延伸到衬底中，第二掺杂区延伸到第一掺杂区并从其中弯曲 并且具有基本上大于第一掺杂浓度的第二掺杂浓度，以及设置在第二掺杂区域下方并具有基本上大于第一掺杂浓度的第三掺杂浓度的第三掺杂区域。 具有第二导电性的源结构设置在基板中并与栅电极相邻。

公开(公告)号：US20130093009A1

公开(公告)日：2013-04-18

申请号：US13271239

申请日：2011-10-12

申请人： Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

发明人： Lu-An Chen ,  Tai-Hsiang Lai ,  Tien-Hao Tang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/41758 ,  H01L27/0277 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/7816

摘要： A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source including a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source.

摘要翻译： 一种形成NMOS晶体管的方法包括：形成P基片; 在P基板上形成N阱; 在N阱上形成N漂移区; 在N漂移区上形成n +漏极; 在所述n +漏极上沿纵向方向形成多个第一触点; 在N阱上形成P体; 在所述P体上形成源极，所述源极包括多个n +掺杂区域和沿着所述纵向排列的至少一个p +掺杂区域; 在所述多个n +掺杂区域和所述至少一个p +掺杂区域上形成多个第二接触; 在P体上形成多孔盖; 以及在所述多晶硅栅极和所述源极之间形成栅极氧化物。