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公开(公告)号：US08318562B2
公开(公告)日：2012-11-27
申请号：US12061358
申请日：2008-04-02
IPC分类号： H01L21/336
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/66462
摘要： Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.
摘要翻译： 一般来说，通过使用高介电强度绝缘包封材料抑制表面闪络来实现半导体器件中的高击穿电压的方法。 在本发明的一个实施例中，通过使用高介电强度绝缘封装材料来抑制AlGaN / GaN异质结构场效应晶体管（HFET）中的表面闪络。 基于III-Nitride的HFET的表面闪络将工作电压限制在远低于GaN击穿电压的水平。
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公开(公告)号：US20090090984A1
公开(公告)日：2009-04-09
申请号：US12061358
申请日：2008-04-02
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/66462
摘要： Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.
摘要翻译： 一般来说，通过使用高介电强度绝缘包封材料抑制表面闪络来实现半导体器件中的高击穿电压的方法。 在本发明的一个实施例中，通过使用高介电强度绝缘封装材料来抑制AlGaN / GaN异质结构场效应晶体管（HFET）中的表面闪络。 基于III-Nitride的HFET的表面闪络将工作电压限制在远低于GaN击穿电压的水平。
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公开(公告)号：US20130062614A1
公开(公告)日：2013-03-14
申请号：US13591140
申请日：2012-08-21
CPC分类号： H01L29/42316 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： An apparatus includes an enhancement mode transistor having multiple Group III-V layers above a substrate and a gate above the Group III-V layers. The gate includes multiple layers of material that form at least a portion of a thyristor. The multiple layers of material may include a first p-type layer of material, an n-type layer of material on the first p-type layer, and a second p-type layer of material on the n-type layer. The multiple layers of material may also include a p-type layer of material, an n-type layer of material on the p-type layer, and a Schottky metal layer on the n-type layer. The enhancement mode transistor may represent a high electron mobility transistor (HEMT) or a heterostructure field effect transistor (HFET).
摘要翻译： 一种装置包括在衬底上方具有多个III-V层的增强型晶体管和在III-V层以上的栅极。 栅极包括形成晶闸管的至少一部分的多层材料。 多层材料可以包括第一p型材料层，第一p型层上的n型材料层和n型层上的第二p型材料层。 多层材料还可以包括p型层材料，p型层上的n型材料层和n型层上的肖特基金属层。 增强型晶体管可以表示高电子迁移率晶体管（HEMT）或异质结构场效应晶体管（HFET）。
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公开(公告)号：US20110095359A1
公开(公告)日：2011-04-28
申请号：US12824075
申请日：2010-06-25
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/42368 , H01L29/66734
摘要： A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions.
摘要翻译： 沟槽金属氧化物半导体场效应晶体管（TMOSFET）包括设置在多个栅极区域之间的多个台面。 每个台面包括漂移区域和身体区域。 台面的宽度在栅极绝缘体区域和体区域之间的界面处是量子阱尺寸的量级。TMOSFET还包括设置在栅极区域与体区域之间的多个栅极绝缘体区域，漂移区域和漏极 地区。 栅极区域和漏极区域之间的栅极绝缘体区域的厚度导致处于OFF状态的栅极 - 漏极电场，其基本上横向有助于消除漂移区域中的电荷。
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公开(公告)号：US10026835B2
公开(公告)日：2018-07-17
申请号：US12824075
申请日：2010-06-25
申请人： Naveen Tipirneni , Deva Pattanayak
发明人： Naveen Tipirneni , Deva Pattanayak
IPC分类号： H01L27/088 , H01L29/78 , H01L29/423 , H01L29/66 , H01L29/08
摘要： A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions.
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公开(公告)号：US09842911B2
公开(公告)日：2017-12-12
申请号：US13484114
申请日：2012-05-30
IPC分类号： H01L31/119 , H01L29/66 , H01L21/266 , H01L29/40 , H01L29/78 , H01L29/06 , H01L29/10
CPC分类号： H01L29/66712 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/1095 , H01L29/404 , H01L29/7811
摘要： In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.
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公开(公告)号：US20130320462A1
公开(公告)日：2013-12-05
申请号：US13484114
申请日：2012-05-30
CPC分类号： H01L29/66712 , H01L21/266 , H01L29/0615 , H01L29/0619 , H01L29/1095 , H01L29/404 , H01L29/7811
摘要： In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.
摘要翻译： 在一个实施例中，半导体器件可以包括包括第一类型掺杂剂的衬底。 半导体器件还可以包括位于衬底上方并且包含比衬底更低浓度的第一类型掺杂剂的外延层。 此外，半导体器件可以包括位于外延层内并包括第二类型掺杂剂的结延伸区域。 此外，半导体器件可以包括与结延伸区物理接触的一组场环，并且包括比结延伸区域更高浓度的第二类型掺杂剂。 此外，半导体器件可以包括与一组场环物理接触的边缘终端结构。
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