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    Selective acknowledgement of RDMA packets
    4.
    发明授权
    Selective acknowledgement of RDMA packets 有权

    公开(公告)号：US10430374B2

    公开(公告)日：2019-10-01

    申请号：US15196088

    申请日：2016-06-29

    申请人： Mellanox Technologies Ltd.

    发明人： Adi Menachem ,  Ariel Shahar ,  Noam Bloch ,  Diego Crupnicoff ,  Michael Kagan

    IPC分类号： G06F15/173 ,  H04L29/06 ,  G06F13/28 ,  H04L1/16 ,  H04L1/18

    摘要： A method for data transfer includes transmitting a sequence of data packets, including at least a first packet and a second packet transmitted subsequently to the first packet, from a first computer over a network to a second computer in a single remote direct memory access (RDMA) data transfer transaction. Upon receipt of the second packet at the second computer without previously having received the first packet, a negative acknowledgment (NAK) packet is sent from the second computer over the network to the first computer, indicating that the first packet was not received. In response to the NAK packet, the first packet is retransmitted from the first computer to the second computer without retransmitting the second packet.

    Prioritized handling of incoming packets by a network interface controller
    5.
    发明申请
    Prioritized handling of incoming packets by a network interface controller 审中-公开

    公开(公告)号：US20180102976A1

    公开(公告)日：2018-04-12

    申请号：US15836869

    申请日：2017-12-10

    申请人： Mellanox Technologies, Ltd.

    发明人： Michael Kagan ,  Noam Bloch

    IPC分类号： H04L12/851 ,  H04L29/00 ,  G06F13/30

    摘要： A network interface controller includes a host interface, which is configured to be coupled to a host processor having a host memory. A network interface is configured to receive data packets from a network, each data packet including a header, which includes header fields, and a payload including data. Packet processing circuitry is configured to process one or more of the header fields and at least a part of the data and to select, responsively at least to the one or more of the header fields, a location in the host memory. The circuitry writes the data to the selected location and upon determining that the processed data satisfies a predefined criterion, asserts an interrupt on the host processor so as to cause the host processor to read the data from the selected location in the host memory.

    Aggregation protocol
    6.
    发明申请
    Aggregation protocol 审中-公开
    聚合协议

    公开(公告)号：US20170063613A1

    公开(公告)日：2017-03-02

    申请号：US15250953

    申请日：2016-08-30

    申请人： Mellanox Technologies Ltd.

    发明人： Gil Bloch ,  Diego Crupnicoff ,  Benny Koren ,  Oded Wertheim ,  Lion Levi ,  Richard Graham ,  Michael Kagan

    IPC分类号： H04L12/24 ,  H04L12/18 ,  H04L12/44

    CPC分类号： H04L12/185 ,  H04L12/44 ,  H04L41/12

    摘要： A switch in a data network is configured to mediate data exchanges among network elements. The apparatus further includes a processor, which organizes the network elements into a hierarchical tree having a root node network element, vertex node network elements child node network elements that include leaf node network elements. The leaf node network elements are originate aggregation data and transmit the aggregation data to respective parent vertex node network elements. The vertex node network elements combine the aggregation data from at least a portion of the child node network elements, and transmit the combined aggregation data from the vertex node network elements to parent vertex node network elements. The root node network element is operative for initiating a reduction operation on the aggregation data.

    摘要翻译： 数据网络中的交换机被配置为中介网元之间的数据交换。 该装置还包括处理器，其将网络元件组织成具有根节点网络元件的分层树，顶点节点网络元素包括叶节点网络元素的子节点网络元素。 叶节点网元是始发聚合数据，并将聚合数据发送到相应的父顶点节点网元。 顶点节点网络元素组合来自至少一部分子节点网元的聚合数据，并将组合聚合数据从顶点节点网元发送到父顶点节点网元。 根节点网元可用于启动对聚合数据的简化操作。

    STORAGE SYSTEM AND SERVER
    7.
    发明申请
    STORAGE SYSTEM AND SERVER 有权
    存储系统和服务器

    公开(公告)号：US20150261434A1

    公开(公告)日：2015-09-17

    申请号：US14215099

    申请日：2014-03-17

    申请人： Mellanox Technologies Ltd.

    发明人： Michael Kagan ,  Noam Bloch ,  Shlomo Raikin ,  Yaron Haviv ,  Idan Burstein

    IPC分类号： G06F3/06 ,  H04L29/08

    CPC分类号： G06F13/28 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0688 ,  G06F13/4221 ,  G06F15/17331 ,  H04L67/10 ,  Y02D10/14 ,  Y02D10/151

    摘要： A data storage system includes a storage server, including non-volatile memory (NVM) and a server network interface controller (NIC), which couples the storage server to a network. A host computer includes a host central processing unit (CPU), a host memory and a host NIC, which couples the host computer to the network. The host computer runs a driver program that is configured to receive, from processes running on the host computer, commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer, and upon receiving a storage access command in accordance with the protocol, to initiate a remote direct memory access (RDMA) operation to be performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.

    摘要翻译： 数据存储系统包括存储服务器，其包括非易失性存储器（NVM）和将存储服务器耦合到网络的服务器网络接口控制器（NIC）。 主计算机包括主机中央处理单元（CPU），主机存储器和主机NIC，其将主计算机耦合到网络。 主计算机运行驱动程序，其被配置为从主机计算机上运行的进程接收根据为访问连接到主计算机的外围组件接口总线的本地存储设备而定义的协议的命令，以及在接收到存储器 访问命令，以启动由主机和服务器NIC执行的远程直接存储器访问（RDMA）操作，以便经由网络在存储服务器上执行由该命令指定的存储事务。

    Direct IO access from a CPU's instruction stream
    8.
    发明申请
    Direct IO access from a CPU's instruction stream 有权
    从CPU的指令流直接访问IO

    公开(公告)号：US20150212817A1

    公开(公告)日：2015-07-30

    申请号：US14608252

    申请日：2015-01-29

    申请人： Mellanox Technologies, Ltd.

    发明人： Shlomo Raikin ,  Noam Bloch ,  Richard Graham ,  Ofer Hayut ,  Michael Kagan ,  Liran Liss

    IPC分类号： G06F9/30 ,  G06F11/22 ,  G06F11/36

    CPC分类号： G06F11/073 ,  G06F9/30043 ,  G06F11/0745 ,  G06F11/0757 ,  G06F11/2236 ,  G06F11/3668

    摘要： A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.

    摘要翻译： 一种使用常规负载和存储直接从本地指令流网络访问远程存储器的方法。 在网络IO访问（网络阶段）不能与计算阶段重叠的情况下，来自指令流的直接网络访问大大降低了CPU处理中的延迟。 该网络被视为可以直接从CPU读取或写入的另一个存储器。 网络访问可以直接从指令流使用常规的负载和存储。 同步网络访问可能有益的示例场景是SHMEM（对称分层存储器访问）用途（程序直接读/写远程内存的位置）以及系统内存（例如DDR）的一部分可以驻留在网络上并使其可访问的情况 通过需求到不同的CPU。

    Direct memory access to storage devices
    9.
    发明授权
    Direct memory access to storage devices 有权
    直接内存访问存储设备

    公开(公告)号：US08949486B1

    公开(公告)日：2015-02-03

    申请号：US13943809

    申请日：2013-07-17

    申请人： Mellanox Technologies Ltd.

    发明人： Michael Kagan ,  Diego Crupnicoff

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： An interface device includes a first proxy interface configured to carry out first direct memory access (DMA) transactions initiated by an input/output (I/O) device and a second proxy interface configured to carry out second DMA transactions initiated by a storage drive. A buffer memory is coupled between the first and second proxy interfaces and configured to temporarily hold data transferred in the first and second DMA transactions. Control logic is configured to invoke the second DMA transactions in response to the first DMA transactions so as to cause the data to be transferred via the buffer between the I/O device and the storage drive.

    摘要翻译： 接口设备包括被配置为执行由输入/输出（I / O）设备发起的第一直接存储器访问（DMA）事务的第一代理接口和被配置为执行由存储驱动器发起的第二DMA事务的第二代理接口。 缓冲存储器耦合在第一和第二代理接口之间并被配置为临时保存在第一和第二DMA事务中传送的数据。 控制逻辑被配置为响应于第一DMA事务来调用第二DMA事务，以便使数据通过I / O设备和存储驱动器之间的缓冲器传送。

    Reducing size of completion notifications
    10.
    发明申请
    Reducing size of completion notifications 有权
    减少完成通知的大小

    公开(公告)号：US20140143454A1

    公开(公告)日：2014-05-22

    申请号：US13682772

    申请日：2012-11-21

    申请人： MELLANOX TECHNOLOGIES LTD.

    发明人： Ofer Hayut ,  Noam Bloch ,  Michael Kagan ,  Ariel Shachar

    IPC分类号： G06F3/01

    CPC分类号： G06F3/016 ,  G06F13/128 ,  G06F13/14

    摘要： A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.

    摘要翻译： 计算机外围设备包括主机接口，其被配置为通过总线与主处理器和主机处理器的系统存储器进行通信。 外围设备中的处理电路被配置为通过在主处理器上运行的客户端进程来接收和执行提交给外围设备的工作项目，并响应于完成工作项目的执行，将完成报告写入系统存储器，包括首次完成 报告第一数据大小和第二数据大小的第二完成报告，其小于第一数据大小。