摘要:
A semiconductor circuit includes a first circuit determining a voltage of a first node in response to the clock signal and the input data signal, a first latch determining a voltage of a second node in response to the clock signal and the voltage of the first node, and a second circuit determining a voltage of a third node in response to the clock signal and the voltage of the second node. The output data signal is provided in response to the voltage of the third node, the clock signal controls a flip-flop operation with respect to the input data signal and the output data signal, and respective voltages are maintained constant at the first node, second node and third node regardless of level transitions in the clock signal so long as a level of the input data signal is maintained constant.
摘要:
A method is provided for programming a flash memory device including memory cells formed in a direction perpendicular to a substrate, a first sub word line connected to first memory cells and selectable by a first selection line, and a second sub word line connected to second memory cells and selectable by a second selection line, the first and second memory cells being formed at the same level and being supplied with a program voltage at the same time. The method includes performing LSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; performing CSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; and performing MSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively.
摘要:
A level-converted and clock-gated latch includes a pulse generator, a level converting unit, and a latch circuit. The pulse generator is provided with a first power-supply voltage and generates a pulse signal having a first voltage level, in response to a clock signal. The level converting unit is provided with a second power-supply voltage and generates an intermediate clock signal having a second voltage level, in response to an inverted clock signal, the clock signal and an enable signal. The latch circuit is provided with the second power-supply voltage, latches the intermediate clock signal, and provides a gated clock signal having the second voltage level. An activation interval of the gated clock signal is controlled based on the enable signal.
摘要:
A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.
摘要:
A flat panel display device including a display panel, a bezel having a substrate to support the display panel and configured to receive the display panel, and a bonding agent disposed between the substrate of the bezel and the display panel. Further, the substrate of the bezel and the display panel may be bonded and fixed to each other. Therefore, it is possible to provide a flat panel display device having a small thickness and capable of improving strength against an external pressure.
摘要:
A semiconductor integrated circuit includes a scan enable (SE) inverter and a clock (CK) inverter on a substrate, a first multiplex part, and a second multiplex part. The SE inverter and the CK inverter are aligned in a first direction. The first multiplex part includes a first wiring and a first transistor, the first wiring is connected to a power supply voltage part of the SE inverter, and the first wiring and the first transistor share a source region contacting the first wiring. The second multiplex part includes a second wiring and a second transistor, the second wiring is connected to a power supply voltage part of the CK inverter, and the second wiring and the second transistor share a source region contacting the second wiring. The SE inverter and the CK inverter are aligned in a first direction to each other.
摘要:
A semiconductor device includes a first circuit applying an enable signal having a first logic level and a clock signal having the first logic level, supplying a first voltage to a first node and converting a voltage level of the first node into a second logic level different from the first logic level, and a second circuit applying an enable signal having the second logic level and a clock signal having the first logic level, supplying a second voltage to a second node different from the first node and converting a voltage level of the second node into the second logic level. The second circuit includes an operation circuit performing a NAND operation on the logic level of the enable signal and the voltage level of the second node, and a switch turned on in response to an output of the operation circuit and supplying the second voltage to the second node.