公开(公告)号：US20140154862A1

公开(公告)日：2014-06-05

申请号：US14174777

申请日：2014-02-06

Applicant: Macronix International Co., Ltd. ,  International Business Machines Corporation

Inventor： Matthew J. Breitwisch ,  Roger W. Cheek ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Eric A. Joseph ,  Alejandro G. Schrott

IPC: H01L45/00

CPC classification number: H01L45/1683 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

Abstract: A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

Abstract translation: 存储单元及其制造方法，其包括沉积在基板上的绝缘材料，形成在绝缘材料内的底部电极，沉积在底部电极上方的多个绝缘层，并且其中至少一个用作中间绝缘层 层。 在中间绝缘层上方的绝缘层中限定通孔。 创建一个通道用于用牺牲隔离物进行蚀刻。 在中间绝缘层中限定孔。 除去中间绝缘层之上的所有绝缘层，并且剩余的孔的整个填充有相变材料。 在相变材料上形成上电极。

公开(公告)号：US08772747B2

公开(公告)日：2014-07-08

申请号：US13867525

申请日：2013-04-22

Applicant: Macronix International Co., Ltd.

Inventor： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

IPC: H01L47/00

CPC classification number: H01L47/00 ,  C23C14/06 ,  C23C14/0623 ,  C23C14/3414 ,  H01L21/06 ,  H01L27/24 ,  H01L45/144 ,  H01L45/1625

Abstract: A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

Abstract translation: 使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。 硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。 对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。 可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

公开(公告)号：US08853047B2

公开(公告)日：2014-10-07

申请号：US14281192

申请日：2014-05-19

Applicant: Macronix International Co., Ltd.

Inventor： Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Chung Hon Lam

IPC: H01L45/00 ,  H01L21/20 ,  H01L27/24

CPC classification number: H01L45/1666 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/124 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1691

Abstract: A fin-type programmable memory cell includes a bottom electrode electrically coupled to an access device, a top electrode, and an L-shaped memory material element electrically coupled to the bottom and top electrodes. A memory array includes an array of such memory cells, electrically coupled to an array of access devices. Method for making a memory cell, includes: forming a dielectric support layer over a bottom electrode, the dielectric support layer having an upper surface; forming a cavity through the dielectric support layer, exposing a surface of the bottom electrode and defining a dielectric support structure having a sidewall; forming a film of memory material over the dielectric support structure and in the cavity; depositing a dielectric spacer layer over the memory material film; forming a dielectric sidewall spacer from the dielectric spacer layer and a memory material structure having a generally horizontal portion underlying the dielectric sidewall spacer and a generally vertical portion between the dielectric sidewall spacer and the sidewall of the dielectric support structure; forming a dielectric fill; planarizing the dielectric fill to expose upper ends of the vertical portion of the memory material structure; depositing a top electrode material over the planarized dielectric fill; and forming a top electrode from the top electrode material and a memory material element from the memory material structure.

公开(公告)号：US08809828B2

公开(公告)日：2014-08-19

申请号：US14179707

申请日：2014-02-13

Applicant: International Business Machines Corporation ,  Macronix International Co., Ltd.

Inventor： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Hsiang-Lan Lung

IPC: H01L21/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683 ,  H01L45/1691

Abstract: An example embodiment disclosed is a phase change memory cell in a semiconductor wafer. The semiconductor wafer includes a first metalization layer (Metal 1). The phase change memory cell includes an insulating substrate defining a non-sublithographic via. The non-sublithographic via is located on the first metalization layer and includes a bottom and a sidewall. Intermediate insulating material is positioned below the insulating substrate. The intermediate insulating material defines a sublithographic aperture passing through the bottom of the non-sublithographic via. A bottom electrode is positioned within the sublithographic aperture, and is composed of conductive non-phase change material. The non-sublithographic via includes phase change material positioned within. The phase change material is electrically coupled to the bottom electrode. A liner is positioned along the sidewall of the non-sublithographic via. The liner is electrically coupled to the phase change material and is composed of the conductive non-phase change material.

Abstract translation: 所公开的示例性实施例是半导体晶片中的相变存储单元。 半导体晶片包括第一金属化层（金属1）。 相变存储单元包括限定非亚光刻通孔的绝缘基板。 非亚光刻通孔位于第一金属化层上并且包括底部和侧壁。 中间绝缘材料位于绝缘基板的下方。 中间绝缘材料限定通过非亚光刻通孔底部的亚光刻孔。 底电极位于亚光刻孔内，由导电非相变材料构成。 非亚光刻通孔包括位于其内的相变材料。 相变材料电耦合到底部电极。 沿着非亚光刻通孔的侧壁定位衬垫。 衬套电耦合到相变材料，并由导电非相变材料组成。

公开(公告)号：US09166165B2

公开(公告)日：2015-10-20

申请号：US14174777

申请日：2014-02-06

Applicant: International Business Machines Corporation ,  Macronix International Co., Ltd.

Inventor： Matthew J. Breitwisch ,  Roger W. Cheek ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Eric A. Joseph ,  Alejandro G. Schrott

IPC: H01L21/00 ,  H01L45/00

CPC classification number: H01L45/1683 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

Abstract: A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

Abstract translation: 存储单元及其制造方法，其包括沉积在基板上的绝缘材料，形成在绝缘材料内的底部电极，沉积在底部电极上方的多个绝缘层，并且其中至少一个用作中间绝缘层 层。 在中间绝缘层上方的绝缘层中限定通孔。 创建一个通道用于用牺牲隔离物进行蚀刻。 在中间绝缘层中限定孔。 去除中间绝缘层之上的所有绝缘层，并且剩余的孔的整个填充有相变材料。 在相变材料上形成上电极。

公开(公告)号：US20140166967A1

公开(公告)日：2014-06-19

申请号：US14179707

申请日：2014-02-13

Applicant: Macronix International Co., Ltd. ,  International Business Machines Corporation

Inventor： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Hsiang-Lan Lung

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683 ,  H01L45/1691

Abstract: An example embodiment disclosed is a phase change memory cell in a semiconductor wafer. The semiconductor wafer includes a first metalization layer (Metal 1). The phase change memory cell includes an insulating substrate defining a non-sublithographic via. The non-sublithographic via is located on the first metalization layer and includes a bottom and a sidewall. Intermediate insulating material is positioned below the insulating substrate. The intermediate insulating material defines a sublithographic aperture passing through the bottom of the non-sublithographic via. A bottom electrode is positioned within the sublithographic aperture, and is composed of conductive non-phase change material. The non-sublithographic via includes phase change material positioned within. The phase change material is electrically coupled to the bottom electrode. A liner is positioned along the sidewall of the non-sublithographic via. The liner is electrically coupled to the phase change material and is composed of the conductive non-phase change material.

Abstract translation: 所公开的示例性实施例是半导体晶片中的相变存储单元。 半导体晶片包括第一金属化层（金属1）。 相变存储单元包括限定非亚光刻通孔的绝缘基板。 非亚光刻通孔位于第一金属化层上并且包括底部和侧壁。 中间绝缘材料位于绝缘基板的下方。 中间绝缘材料限定通过非亚光刻通孔底部的亚光刻孔。 底电极位于亚光刻孔内，由导电非相变材料构成。 非亚光刻通孔包括位于其内的相变材料。 相变材料电耦合到底部电极。 沿着非亚光刻通孔的侧壁定位衬垫。 衬套电耦合到相变材料，并由导电非相变材料组成。