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    Reference-Less Voltage Controlled Oscillator (VCO) Calibration
    3.
    发明申请
    Reference-Less Voltage Controlled Oscillator (VCO) Calibration 有权
    无参考电压控制振荡器（VCO）校准

    公开(公告)号：US20120313714A1

    公开(公告)日：2012-12-13

    申请号：US13158075

    申请日：2011-06-10

    申请人： Mahyar Kargar ,  Siavash Fallahi ,  Namik Kocaman ,  Afshin Momtaz

    发明人： Mahyar Kargar ,  Siavash Fallahi ,  Namik Kocaman ,  Afshin Momtaz

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0807 ,  H03L7/00 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/113 ,  H03L2207/06 ,  H04L7/0004 ,  H04L7/033

    摘要： Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.

    摘要翻译： 提供了无参考压控振荡器（VCO）校准的实施例。 实施例包括VCO校准模块，其使用来自频率检测器的一个或多个信号来自动选择适当的VCO频带并使VCO时钟频率接近于数据速率。 VCO校准模块使用校准代码校准VCO。 在实施例中，使用频率搜索方案来确定校准码，该频率搜索方案包括确定适当的VCO频带的发现阶段以及二进制搜索阶段和监视阶段，以选择使VCO时钟频率最接近数据的校准码 率。

    Reference-less voltage controlled oscillator (VCO) calibration
    4.
    发明授权
    Reference-less voltage controlled oscillator (VCO) calibration 有权
    无参考压控振荡器（VCO）校准

    公开(公告)号：US09281828B2

    公开(公告)日：2016-03-08

    申请号：US13158075

    申请日：2011-06-10

    申请人： Mahyar Kargar ,  Siavash Fallahi ,  Namik Kocaman ,  Afshin Momtaz

    发明人： Mahyar Kargar ,  Siavash Fallahi ,  Namik Kocaman ,  Afshin Momtaz

    IPC分类号： H03L7/00 ,  H03L7/087 ,  H03L7/091 ,  H03L7/08 ,  H03L7/099 ,  H03L7/113 ,  H04L7/00 ,  H04L7/033

    CPC分类号： H03L7/0807 ,  H03L7/00 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/113 ,  H03L2207/06 ,  H04L7/0004 ,  H04L7/033

    摘要： Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.

    摘要翻译： 提供了无参考压控振荡器（VCO）校准的实施例。 实施例包括VCO校准模块，其使用来自频率检测器的一个或多个信号来自动选择适当的VCO频带并使VCO时钟频率接近于数据速率。 VCO校准模块使用校准代码校准VCO。 在实施例中，使用频率搜索方案来确定校准码，该频率搜索方案包括确定适当的VCO频带的发现阶段以及二进制搜索阶段和监视阶段，以选择使VCO时钟频率最接近数据的校准码 率。

    Transition insensitive timing recovery method and apparatus
    7.
    发明授权
    Transition insensitive timing recovery method and apparatus 失效
    过渡不敏感的定时恢复方法和装置

    公开(公告)号：US07170964B2

    公开(公告)日：2007-01-30

    申请号：US10355848

    申请日：2003-01-31

    申请人： Namik Kocaman ,  Afshin Momtaz

    发明人： Namik Kocaman ,  Afshin Momtaz

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0331 ,  H03L7/091 ,  H03L7/093

    摘要： A timing recovery circuit comprises a data-driven phase detector and a digital loop filter. The data-driven phase detector is operably coupled to determine at least a phase difference between an input signal and a feedback clock signal to produce a difference signal. Determining the phase difference can comprise digitally determining a timing difference between the input signal and the feedback clock signal, digitally determining a transition of the input signal to produce a transition detect signal, and digitally updating the timing difference based on the transition detect signal and the feedback clock signal. The timing difference can be digitally updated by pre-filtering the timing difference BY TAKING EVERY N TRANSITON OR AVERAGE OF EVERY N TRANSITIONS at a digital pre-filter, based on a pre-filter clock signal produced from the transition detect signal and the feedback clock signal, to produce the difference signal. The loop filter is operably coupled to filter the difference signal to produce a control voltage.

    摘要翻译： 定时恢复电路包括数据驱动相位检测器和数字环路滤波器。 数据驱动相位检测器可操作地耦合以确定输入信号和反馈时钟信号之间的至少一个相位差，以产生差分信号。 确定相位差可以包括数字地确定输入信号和反馈时钟信号之间的定时差，数字地确定输入信号的转变以产生转换检测信号，并且基于转换检测信号和数字地更新定时差 反馈时钟信号。 基于从转换检测信号和反馈时钟产生的预滤波器时钟信号，通过对数字预滤波器进行每次N个转换的每次N次转换或每次N个转换的平均值来预定时器差异，可以对定时差异进行数字更新 信号，产生差分信号。 环路滤波器可操作地耦合以滤除差分信号以产生控制电压。

    Automatic gain control using multi-comparators
    8.
    发明申请
    Automatic gain control using multi-comparators 失效
    使用多比较器进行自动增益控制

    公开(公告)号：US20060261895A1

    公开(公告)日：2006-11-23

    申请号：US11135208

    申请日：2005-05-23

    申请人： Namik Kocaman ,  Afshin Momtaz

    发明人： Namik Kocaman ,  Afshin Momtaz

    IPC分类号： H03G3/10

    CPC分类号： H03G3/3052 ,  H03G3/001 ,  H03G3/3036

    摘要： A method and apparatus for an automatic gain control (AGC) loop that utilizes multiple comparators to provide constant bandwidth tracking and step response, as well as fine granularity for decision directed convergence. In one embodiment, an odd number of comparators is used with square-law scaling at the output to achieve constant bandwidth step response for a wide range of input amplitude changes.

    摘要翻译： 一种用于自动增益控制（AGC）回路的方法和装置，其利用多个比较器来提供恒定的带宽跟踪和阶跃响应，以及用于决策定向收敛的细粒度。 在一个实施例中，使用奇数比较器，在输出处使用平方律缩放来实现宽范围的输入幅度变化的恒定带宽阶跃响应。

    Digitally controlled threshold adjustment circuit
    9.
    发明申请
    Digitally controlled threshold adjustment circuit 有权
    数字控制阈值调节电路

    公开(公告)号：US20060244506A1

    公开(公告)日：2006-11-02

    申请号：US11117767

    申请日：2005-04-28

    申请人： Namik Kocaman ,  Afshin Momtaz

    发明人： Namik Kocaman ,  Afshin Momtaz

    IPC分类号： H03L5/00

    CPC分类号： H03K5/151 ,  H03K5/003 ,  H03K5/086

    摘要： A threshold adjustment circuit including: a current DAC for supplying or sinking a varying current; a differential pair of thin oxide transistors coupled to the DAC and coupled together at a common source node; a power supply for providing a supply voltage having a voltage level above reliability of the thin oxide transistors; and a third transistor for maintaining voltage of the common source node above a predetermined level and to disable the threshold adjustment circuit. The bulk and source of each of the differential pair thin oxide transistors is coupled to the common source node and each of the differential pair thin oxide transistors is switched by a signal to keep each of the differential pair thin oxide transistors in saturation region.

    摘要翻译： 一种阈值调整电路，包括：用于提供或吸收变化电流的电流DAC; 耦合到DAC并在公共源节点处耦合在一起的薄氧化物晶体管的差分对; 用于提供具有高于薄氧化物晶体管的可靠性的电压电平的电源电压的电源; 以及第三晶体管，用于将公共源节点的电压维持在预定电平以上并禁止阈值调整电路。 每个差分对薄氧化物晶体管的体积和源极耦合到公共源节点，并且每个差分对薄氧化物晶体管被信号切换，以将每个差分对薄氧化物晶体管保持在饱和区域。

    High speed, low power non-return-to-zero/return-to-zero output driver
    10.
    发明授权
    High speed, low power non-return-to-zero/return-to-zero output driver 有权
    高速，低功耗非归零/归零输出驱动器

    公开(公告)号：US07973681B2

    公开(公告)日：2011-07-05

    申请号：US12567841

    申请日：2009-09-28

    申请人： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

    发明人： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

    IPC分类号： H03M7/12

    CPC分类号： H04L25/0276 ,  H03M5/04 ,  H04L25/0274 ,  H04L25/0282 ,  H04L25/0284

    摘要： A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

    摘要翻译： 门控逻辑接收非归零（NRZ）输入信号，并且在NRZ工作模式下将NRZ输入信号耦合为NRZ输出信号，并将NRZ输入信号转换为零（ RZ）输出信号。 耦合到门控逻辑的电路接收时钟信号并将时钟信号耦合到门控逻辑，以将RZ输入信号转换为RZ工作模式的RZ输出信号。 在NRZ工作模式下，电路解耦时钟信号，并在门控逻辑上放置预定的信号状态，以通过NRZ输入信号作为NRZ输出信号。 电路接收选择信号以在NRZ和RZ工作模式之间进行选择，并通过控制门控逻辑的时钟信号获得NRZ和RZ模式。