公开(公告)号：US08103945B2

公开(公告)日：2012-01-24

申请号：US11959551

申请日：2007-12-19

申请人： Makiko Yamamoto ,  Satoshi Okada ,  Toshiyuki Miyauchi ,  Takashi Yokokawa

发明人： Makiko Yamamoto ,  Satoshi Okada ,  Toshiyuki Miyauchi ,  Takashi Yokokawa

IPC分类号： G06F11/00

CPC分类号： H03M13/114 ,  H03M13/1111 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2936 ,  H03M13/2948 ,  H03M13/3905 ,  H03M13/4146

摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.

摘要翻译： 一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播 值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播 可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。

公开(公告)号：US20100299572A1

公开(公告)日：2010-11-25

申请号：US12743649

申请日：2008-11-18

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H04L27/3416 ,  H03M13/036 ,  H03M13/1165 ,  H03M13/255 ,  H03M13/271 ,  H03M13/356 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/3488 ,  H04L27/36

摘要： A data processing apparatus, a data processing method, an encoding apparatus and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve the tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of ⅔, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by bi and yi, respectively, replacement of allocating b0 to y15, b1 to y7, b2 to y1, b3 to y5, b4 to y6, b5 to y13, b6 to y11, b7 to y9, b8 to y8, b9 to y14, b10 to y12, b11 to y3, b12 to y0, b13 to y10, b14 to y4 and b15 to y2.

摘要翻译： 可以应用于例如用于发送LDPC码等的传输系统的数据处理装置，数据处理方法，编码装置和编码方法，并且可以提高对误差的容限。 在DVB-S.2中规定的并且具有64,800的码长和an的编码率的LDPC码中，替换mb个码比特，并且替换后的码比特成为b符号的符号比特。 当m为8且b为2时，分别用b 1和y i表示从8×2码位的最高有效位和2个连续符号的8×2符号位的第i + 1位，将b0分配给 y15，b1〜y7，b2〜y1，b3〜y5，b4〜y6，b5〜y13，b6〜y11，b7〜y9，b8〜y8，b9〜y14，b10〜y12，b11〜y3，b12〜y0， b13〜y10，b14〜y4，b15〜y2。

公开(公告)号：US20100275101A1

公开(公告)日：2010-10-28

申请号：US12744400

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1165 ,  H03M13/036 ,  H03M13/255 ,  H03M13/2703 ,  H03M13/271 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/3416 ,  H04L27/3488

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.

摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中取代mb比特，并将替换后的码比特设置为b符号的符号比特。 根据分配规则，分别将代码比特和符号比特的组合作为码比特组和符号比特组分别设定为组合的任何编码比特组 以及要分配码位组的码位的符号位的符号位组，以及代码位和符号位的位编号。

公开(公告)号：US08578237B2

公开(公告)日：2013-11-05

申请号：US12744400

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/036 ,  H03M13/255 ,  H03M13/2703 ,  H03M13/271 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/3416 ,  H04L27/3488

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.

摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中取代mb比特，并将替换后的码比特设置为b符号的符号比特。 根据分配规则，分别将代码比特和符号比特的组合作为码比特组和符号比特组分别设定为组合的任何编码比特组 以及要分配码位组的码位的符号位的符号位组，以及代码位和符号位的位编号。

公开(公告)号：US08499214B2

公开(公告)日：2013-07-30

申请号：US12743398

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

IPC分类号： H03M13/00

CPC分类号： H04L27/2647 ,  H03M13/033 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/2906 ,  H03M13/356 ,  H03M13/6552 ,  H03M13/6555

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12×1 code bits and the 12×1 symbol bits of one symbol are represented as bits bi and yi, replacement for allocating, for example, b0 to y8, b1 to y0, b2 to y6, b3 to y1, b4 to y4, b5 to y5, b6 to y2, b7 to y3, b8 to y7, b9 to y10, b10 to y11 and b11 to y9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.

摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器25根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中替换mb比特，并将替换后的码比特设置为b符号的符号比特。 例如，当m为12且b为1时，其中来自12×1码位的最高有效位的第i + 1位和一个符号的12×1符号位表示为位bi和yi，替换为 分配例如b0至y8，b1至y0，b2至y6，b3至y1，b4至y4，b5至y5，b6至y2，b7至y3，b8至y7，b9至y10，b10至y11和b11 到y9进行。 本发明可以应用于例如用于发送LDPC码等的传输系统。

公开(公告)号：US08335964B2

公开(公告)日：2012-12-18

申请号：US12743384

申请日：2008-11-25

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

IPC分类号： G06F11/00

CPC分类号： H04L27/3416 ,  H03M13/036 ,  H03M13/1165 ,  H03M13/255 ,  H03M13/271 ,  H03M13/356 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/3488 ,  H04L27/36

摘要： A data processing apparatus, a data processing method, an encoding apparatus, and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of 2/3, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by bi and yi, respectively, replacement of allocating b0 to y15, b1 to y7, b2 to y1, b3 to y5, b4 to y6, b5 to y13, b6 to y11, b7 to y9, b8 to y8, b9 to y14, b10 to y12, b11 to y3, b12 to y0, b13 to y10, b14 to y4 and b15 to y2.

摘要翻译： 可以应用于例如用于发送LDPC码的传输系统等的数据处理装置，数据处理方法，编码装置和编码方法，并且可以改善对误差的容限。 在DVB-S.2中规定的并且具有64,800的码长和2/3的编码速率的LDPC码中，替换mb个码比特，并且替换后的码比特成为b符号的符号比特。 当m为8且b为2时，分别用b 1和y i表示从8×2码位的最高有效位和2个连续符号的8×2符号位的第i + 1位，将b0分配给 y15，b1〜y7，b2〜y1，b3〜y5，b4〜y6，b5〜y13，b6〜y11，b7〜y9，b8〜y8，b9〜y14，b10〜y12，b11〜y3，b12〜y0， b13〜y10，b14〜y4，b15〜y2。

公开(公告)号：US20100269019A1

公开(公告)日：2010-10-21

申请号：US12743398

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H04L27/2647 ,  H03M13/033 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/2906 ,  H03M13/356 ,  H03M13/6552 ,  H03M13/6555

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12×1 code bits and the 12×1 symbol bits of one symbol are represented as bits bi and yi, replacement for allocating, for example, b0 to y8, b1 to y0, b2 to y6, b3 to y1, b4 to y4, b5 to y5, b6 to y2, b7 to y3, b8 to y7, b9 to y10, b10 to y11 and b11 to y9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.

摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器25根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中替换mb比特，并将替换后的码比特设置为b符号的符号比特。 例如，当m为12且b为1时，其中来自12×1码位的最高有效位的第i + 1位和一个符号的12×1符号位表示为位bi和yi，替换为 分配例如b0至y8，b1至y0，b2至y6，b3至y1，b4至y4，b5至y5，b6至y2，b7至y3，b8至y7，b9至y10，b10至y11和b11 到y9进行。 本发明可以应用于例如用于发送LDPC码等的传输系统。

公开(公告)号：US20100281329A1

公开(公告)日：2010-11-04

申请号：US12743487

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1165 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/2703 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/6552 ,  H03M13/6555 ,  H04L1/0057

摘要： The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors.Where two or more bits of an LDPC (Low Density Parity Check) code are set as one symbol and are mapped to 214 or 216 signal points, a column twist interleaver 24 carries out, as a re-arrangement process for re-arranging code bits of an LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not included in one symbol, column twist interleave of changing the writing starting position when code bits are written in a column direction of a memory for each column of the memory. The present invention can be applied, for example, to a transmission apparatus for transmitting an LDPC code.

摘要翻译： 本发明涉及一种数据处理装置，数据处理方法和程序，其可以将LDPC码的码位的容限提高到错误。 当LDPC（低密度奇偶校验）码的两个或多个比特被设置为一个符号并被映射到214或216个信号点时，列扭曲交织器24执行用于重新排列码位的重新排列处理 使得与包括在奇偶校验矩阵的一个任意行中的值1相对应的多个码位不包括在一个符号中的LDPC码，当码位被写入列时改变写入起始位置的列扭曲交织 存储器的每列的存储器方向。 本发明可以应用于例如用于发送LDPC码的发送装置。

公开(公告)号：US08489955B2

公开(公告)日：2013-07-16

申请号：US12743487

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/2703 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/6552 ,  H03M13/6555 ,  H04L1/0057

摘要： The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors.Where two or more bits of an LDPC (Low Density Parity Check) code are set as one symbol and are mapped to 214 or 216 signal points, a column twist interleaver 24 carries out, as a re-arrangement process for re-arranging code bits of an LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not included in one symbol, column twist interleave of changing the writing starting position when code bits are written in a column direction of a memory for each column of the memory. The present invention can be applied, for example, to a transmission apparatus for transmitting an LDPC code.

摘要翻译： 本发明涉及一种数据处理装置，数据处理方法和程序，其可以将LDPC码的码位的容限提高到错误。 当LDPC（低密度奇偶校验）码的两个或多个比特被设置为一个符号并被映射到214或216个信号点时，列扭曲交织器24执行用于重新排列码位的重新排列处理 使得与包括在奇偶校验矩阵的一个任意行中的值1相对应的多个码位不包括在一个符号中的LDPC码，当码位被写入列时改变写入起始位置的列扭曲交织 存储器的每列的存储器方向。 本发明可以应用于例如用于发送LDPC码的发送装置。

公开(公告)号：US08464122B2

公开(公告)日：2013-06-11

申请号：US12743398

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

IPC分类号： H03M13/00

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12×1 code bits and the 12×1 symbol bits of one symbol are represented as bits bi and yi, replacement for allocating, for example, b0 to y8, b1 to y0, b2 to y6, b3 to y1, b4 to y4, b5 to y5, b6 to y2, b7 to y3, b8 to y7, b9 to y10, b10 to y11 and b11 to y9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.