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    High withstand voltage type semiconductor device having an isolation region
    2.
    发明授权
    High withstand voltage type semiconductor device having an isolation region 失效
    具有隔离区域的高耐压型半导体器件

    公开(公告)号：US5644157A

    公开(公告)日：1997-07-01

    申请号：US653924

    申请日：1996-05-22

    申请人： Makio Iida ,  Shoji Miura ,  Takayuki Sugisaka ,  Toshio Sakakibara ,  Osamu Ishihara

    发明人： Makio Iida ,  Shoji Miura ,  Takayuki Sugisaka ,  Toshio Sakakibara ,  Osamu Ishihara

    IPC分类号： H01L21/762 ,  H01L29/73 ,  H01L29/732 ,  H01L27/06 ,  H01L29/80

    CPC分类号： H01L29/7317 ,  H01L21/76264 ,  H01L29/7322 ,  H01L21/76275 ,  H01L21/76286

    摘要： A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.

    摘要翻译： 能兼容地实现耐压提高和集成度的半导体装置。 掩埋集电极区域3和集电极耐压区域4之间的PN结经受反向偏压，并且PN结中的耗尽层到达介电隔离区域9a，该介电隔离区域9a介电地隔离集电极耐压区域4的侧面。 与其间的侧绝缘隔离区域9a相邻的集电极耐电压的周向半导体区域14具有接近于基极区域5处的电位，而不是埋藏集电极区域3的电位。结果， 耗尽层受到基极区域5和周围半导体区域14两者的低电位的影响。这减轻了基部区域5的侧面与其底部之间的角部附近的静电聚焦，约束 雪崩击穿，并提高耐压。

    Semiconductor device provided with isolation region
    3.
    发明授权
    Semiconductor device provided with isolation region 失效
    具有隔离区域的半导体器件

    公开(公告)号：US5449946A

    公开(公告)日：1995-09-12

    申请号：US208119

    申请日：1994-03-09

    申请人： Toshio Sakakibara ,  Makio Iida ,  Takayuki Sugisaka ,  Shoji Miura

    发明人： Toshio Sakakibara ,  Makio Iida ,  Takayuki Sugisaka ,  Shoji Miura

    IPC分类号： H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/822 ,  H01L27/04 ,  H01L29/06 ,  H01L27/02

    CPC分类号： H01L21/76264 ,  H01L21/743 ,  H01L21/763 ,  H01L21/76275 ,  H01L21/76286

    摘要： A semiconductor device is provided in which a contact is very simply formed on conductive material for capacitive coupling prevention. Two silicon substrates are bonded through a silicon oxide film. And a trench extending to the silicon oxide film is formed in one of silicon substrates so as to isolate between plural circuit elements from each other, and islands for circuit element formation are compartmently formed by the trench. A silicon oxide film is formed on an outer periphery portion of the islands for circuit element formation. Furthermore, an island for capacitive coupling prevention is formed by the silicon substrate between the islands for circuit element formation and is applied thereto to be maintained in an electric potential of constant.

    摘要翻译： 提供了一种半导体器件，其中在导电材料上非常简单地形成接触，以防止电容耦合。 两个硅衬底通过氧化硅膜结合。 并且在硅基板之一中形成延伸到氧化硅膜的沟槽，以便在多个电路元件之间彼此隔离，并且通过沟槽隔室形成用于电路元件形成的岛。 在用于电路元件形成的岛的外周部分上形成氧化硅膜。 此外，用于电容耦合防止的岛由用于电路元件形成的岛之间的硅衬底形成，并且被施加到其上以保持恒定的电位。

    Dielectric isolated type semiconductor device provided with bipolar element
    4.
    发明授权
    Dielectric isolated type semiconductor device provided with bipolar element 失效
    具有双极元件的绝缘隔离型半导体器件

    公开(公告)号：US5592015A

    公开(公告)日：1997-01-07

    申请号：US547740

    申请日：1995-10-26

    申请人： Makio Iida ,  Tadashi Shibata ,  Takayuki Sugisaka ,  Shoji Miura ,  Toshio Sakakibara

    发明人： Makio Iida ,  Tadashi Shibata ,  Takayuki Sugisaka ,  Shoji Miura ,  Toshio Sakakibara

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/762 ,  H01L21/763 ,  H01L27/02 ,  H01L29/732 ,  H01L29/00 ,  H01L23/58

    CPC分类号： H01L29/7322 ,  H01L21/76264 ,  H01L21/763 ,  H01L27/0248 ,  H01L21/76286

    摘要： A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.

    摘要翻译： 提供一种半导体器件，其使得高耐压双极晶体管变小，并防止晶体管的开关速度的劣化。 在硅衬底上形成硅氧化物层，在氧化硅层上形成由隔离沟侧向隔离的一种导电型半导体岛。 在半导体岛的外周部形成有氧化硅膜，以埋置沟槽。 在半导体岛中，形成双极晶体管，即另一种导电型的基极区域，在基极区域形成一个导电型的发射极区域，并进一步形成一种导电型的集电极区域。 在半导体岛中，进一步形成用于提取施加恒定电位的过量载流子的另一导电类型的扩散区域。

    Dielectric isolated type semiconductor device
    5.
    发明授权
    Dielectric isolated type semiconductor device 失效
    绝缘隔离型半导体器件

    公开(公告)号：US5557134A

    公开(公告)日：1996-09-17

    申请号：US341977

    申请日：1994-11-16

    申请人： Takayuki Sugisaka ,  Toshio Sakakibara ,  Shoji Miura ,  Makio Iida

    发明人： Takayuki Sugisaka ,  Toshio Sakakibara ,  Shoji Miura ,  Makio Iida

    IPC分类号： H01L21/322 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L29/73 ,  H01L29/732 ,  H01L29/866 ,  H01L29/00

    CPC分类号： H01L21/76264 ,  H01L21/3226 ,  H01L21/763 ,  H01L29/7317 ,  H01L29/732 ,  H01L21/76275 ,  H01L21/76286

    摘要： A dielectric isolated type semiconductor device which can achieve a reduction in crystalline defects by means of a simple production process is provided. High-concentration regions are formed as active regions on a surface portion of an islandish semiconductor region which is isolated from an adjacent semiconductor region by means of an isolation trench. According to a first aspect of the present invention, an N type crystalline defect suppression region doped at a high concentration and deeper than the high-concentration regions is formed over the entire surface of an adjacent semiconductor region. According to a second aspect of the present invention, a high-concentration N type crystalline defect suppression region is provided on a surface portion of a P type high-concentration region is formed with identical structure and by an identical production process. By means of these N type regions, crystalline defects are reduced.

    摘要翻译： 提供了一种能够通过简单的制造工艺实现结晶缺陷降低的绝缘隔离型半导体器件。 在通过隔离沟槽与相邻的半导体区域隔离的岛状半导体区域的表面部分上形成高浓度区域作为有源区域。 根据本发明的第一方面，在相邻的半导体区域的整个表面上形成了在高浓度区域和高浓度区域掺杂的N型晶体缺陷抑制区域。 根据本发明的第二方面，在P型高浓度区域的表面部分上形成高浓度的N型结晶缺陷抑制区域，其结构相同，生产方法相同。 通过这些N型区域，晶体缺陷减少。

    Method for fabrication of semiconductor device
    7.
    发明授权
    Method for fabrication of semiconductor device 失效
    半导体器件制造方法

    公开(公告)号：US5480832A

    公开(公告)日：1996-01-02

    申请号：US75514

    申请日：1993-10-21

    申请人： Shoji Miura ,  Takayuki Sugisaka ,  Atsushi Komura ,  Toshio Sakakibara

    发明人： Shoji Miura ,  Takayuki Sugisaka ,  Atsushi Komura ,  Toshio Sakakibara

    IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L21/76

    CPC分类号： H01L21/763 ,  H01L21/76264 ,  H01L21/76802 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286 ,  Y10S148/05 ,  Y10S148/135 ,  Y10S438/977

    摘要： An object of the invention is to prevent the occurrence of breaking or short-circuiting of a wiring caused by a difference in level in an isolation trench area formed in an SOI substrate. An oxide film is formed for a pad on the main surface of an SOI layer formed on an insulating substrate, a silicon nitride film are formed and an SiO.sub.2 film in order, then an isolation trench reaching to the insulating substrate is by means of an R.I.E process using the SiO.sub.2 film as a mask. Thereafter an insulating film is formed on an inside wall of the isolation trench by means of thermal oxidation, the isolation trench is filled with polysilicon, the polysilicon is etched back while controlling the etching so that the top of the polysilicon in the isolation trench remains higher than the top of the silicon nitride film, an extra part of the polysilicon deposited on the surface of the substrate, is removed and then the SiO.sub.2 film used as a mask when forming the isolation trench is etched off using the polysilicon in the isolation trench and the silicon nitride film as an etching stopper. In this manner, since the SiO.sub.2 film used as a mask is etched off after filling the isolation trench with polysilicon, the oxide film for isolating between the substrates is not etched when removing the mask film. Moreover since the polysilicon is the isolation trench and the silicon nitride film act as an etching stopper when etching off the SiO.sub.2 film used as a mask, the oxide film for a pad existing thereunder and the insulating film formed on an inside wall of the trench can also be prevented from being etched and a flatness at an isolation trench area is not deteriorated.

    摘要翻译： PCT No.PCT / JP92 / 01326 Sec。 371日期：1993年10月21日 102（e）日期1993年10月21日PCT提交1992年10月12日PCT公布。 公开号WO93 / 08596 日期：1993年04月29日。本发明的目的在于防止在SOI衬底中形成的隔离沟槽区域中的电平差引起的布线断裂或短路。 在绝缘基板上形成的SOI层的主表面上形成氧化膜，依次形成氮化硅膜和SiO 2膜，然后通过RIE到达绝缘基板的隔离沟槽 使用SiO 2膜作为掩模。 此后，通过热氧化在隔离沟槽的内壁上形成绝缘膜，隔离沟槽填充有多晶硅，在控制蚀刻的同时蚀刻多晶硅，使得隔离沟槽中的多晶硅的顶部保持较高 除去氮化硅膜的顶部，去除沉积在衬底表面上的多晶硅的额外部分，然后使用隔离沟槽中的多晶硅蚀刻掉形成隔离沟槽时用作掩模的SiO 2膜， 作为蚀刻停止层的氮化硅膜。 以这种方式，由于在用多晶硅填充隔离沟槽之后蚀刻用作掩模的SiO 2膜，因此在去除掩模膜时不会蚀刻用于隔离的氧化膜。 此外，由于多晶硅是隔离沟槽，并且氮化硅膜在蚀刻掉用作掩模的SiO 2膜时用作蚀刻阻挡层，所以存在于其上的垫的氧化膜和形成在沟槽的内壁上的绝缘膜 也防止蚀刻，并且隔离沟槽区域的平坦度不会劣化。

    SOI semiconductor device and method of producing same wherein warpage is reduced in the semiconductor device
    8.
    发明授权
    SOI semiconductor device and method of producing same wherein warpage is reduced in the semiconductor device 失效
    SOI半导体器件及其制造方法，其中在半导体器件中翘曲减小

    公开(公告)号：US5599722A

    公开(公告)日：1997-02-04

    申请号：US346255

    申请日：1994-11-23

    申请人： Takayuki Sugisaka ,  Shoji Miura ,  Toshio Sakakibara

    发明人： Takayuki Sugisaka ,  Shoji Miura ,  Toshio Sakakibara

    IPC分类号： H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/265 ,  H01L21/302

    CPC分类号： H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286

    摘要： A trench isolation junction type SOI semiconductor device which reduces substrate warpage while suppressing increase in production steps and a method for producing the same are disclosed. A junction substrate is formed by bonding a semiconductor substrate having an outer insulation film on a non-junction main surface with a semiconductor layer with an inner insulation film sandwiched therebetween. After forming a silicon nitride film as a mask for the purpose of forming a trench in the semiconductor layer, silicon nitride film accumulated on the outer insulation film is removed. By doing this, warpage of the semiconductor substrate due to discrepancies in the thermal expansion rates of the rigid silicon nitride film and semiconductor substrate can be prevented. In a junction type SOI semiconductor device formed via the method, an outer insulation film of identical thickness and identical density to an inner insulation film is formed on a non-junction main surface (i.e., rear surface) of a semiconductor substrate. By doing this, warpage of the semiconductor substrate can be prevented.

    摘要翻译： 公开了一种在抑制生产步骤增加的同时降低衬底翘曲的沟槽隔离结型SOI半导体器件及其制造方法。 通过在非接合主表面上具有外绝缘膜的半导体衬底与夹在其间的内绝缘膜的半导体层结合来形成接合衬底。 在形成用于在半导体层中形成沟槽的掩模的氮化硅膜之后，除去积聚在外绝缘膜上的氮化硅膜。 通过这样做，可以防止由于刚性氮化硅膜和半导体衬底的热膨胀率的差异导致的半导体衬底的翘曲。 在通过该方法形成的结型SOI半导体器件中，在半导体衬底的非接合主表面（即后表面）上形成具有相同厚度和与内绝缘膜相同密度的外绝缘膜。 通过这样做，可以防止半导体衬底的翘曲。