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62 条记录 (耗时 0.029 秒)

    Semiconductor device and manufacturing method thereof
    4.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US06242787B1

    公开(公告)日：2001-06-05

    申请号：US08748896

    申请日：1996-11-15

    申请人： Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

    发明人： Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

    IPC分类号： H01L2976

    CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0623 ,  H01L27/085 ,  H01L29/063 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66674 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7824 ,  H01L29/7835

    摘要： A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

    摘要翻译： 一种包括减小表面场强度型LDMOS晶体管的半导体器件，其可以防止当向其漏极施加反向电压时在沟道形成部分处的元件的击穿。 在N型衬底中形成P阱和N阱以产生双阱结构，其中源极被设置为与N型衬底的电位相等。 N阱的漂移区域具有掺杂浓度以满足所谓的RESURF条件，其可以提供高的击穿电压低导通电阻。 当向漏极施加反向电压时，包括N阱，P阱和N型衬底的寄生双极晶体管形成朝向衬底的通电路径，使得元件在沟道形成时击穿 在施加反向电压时部分是可避免的。

    Constant voltage circuit with a substitute circuit in case of input voltage lowering
    6.
    发明授权
    Constant voltage circuit with a substitute circuit in case of input voltage lowering 有权
    在输入电压降低的情况下，带有替代电路的恒压电路

    公开(公告)号：US06465996B2

    公开(公告)日：2002-10-15

    申请号：US09799106

    申请日：2001-03-06

    申请人： Junichi Nagata ,  Kiyoshi Yamamoto ,  Hirokazu Itakura ,  Masahiro Kitagawa ,  Hiroyuki Ban ,  Hiroyuki Kawabata ,  Shinichi Maeda

    发明人： Junichi Nagata ,  Kiyoshi Yamamoto ,  Hirokazu Itakura ,  Masahiro Kitagawa ,  Hiroyuki Ban ,  Hiroyuki Kawabata ,  Shinichi Maeda

    IPC分类号： G05F316

    CPC分类号： H02J7/0063

    摘要： A constant voltage circuit robust to the input voltage lowering is disclosed. The invention is applied to a constant voltage circuit fed with an input voltage through first and second power conductors for transferring the input voltage to a load as an output voltage through an output transistor. An inventive constant voltage circuit is provided with a substitute circuit, responsive to a detection of the lowing of the input voltage to a predetermined voltage, for providing a substitute output path that is connected in parallel with the output transistor. Doing this minimize the degree of lowering of the second voltage due to the lowering of said first voltage. The output transistor may be nay of NPN and PNP transistors and P-type and N-type MOS FETs.

    摘要翻译： 公开了对输入电压降低稳健的恒定电压电路。 本发明应用于通过第一和第二电力导体馈送输入电压的恒压电路，用于通过输出晶体管将输入电压传送到负载作为输出电压。 本发明的恒压电路具有替代电路，响应于将输入电压降低到预定电压，以提供与输出晶体管并联连接的替代输出路径。 这样做使得由于所述第一电压的降低而使第二电压降低的程度最小化。 输出晶体管可以是NPN和PNP晶体管以及P型和N型MOS FET。

    Reference voltage generating circuit having reduced current consumption with varying loads
    7.
    发明授权
    Reference voltage generating circuit having reduced current consumption with varying loads 失效
    参考电压发生电路具有随着负载变化而具有降低的电流消耗

    公开(公告)号：US5719522A

    公开(公告)日：1998-02-17

    申请号：US814935

    申请日：1997-03-12

    申请人： Mitsuhiro Saitou ,  Hajime Ito ,  Kiyoshi Yamamoto ,  Hiroyuki Ban

    发明人： Mitsuhiro Saitou ,  Hajime Ito ,  Kiyoshi Yamamoto ,  Hiroyuki Ban

    IPC分类号： G05F3/30 ,  G05F3/22 ,  G06F1/26 ,  G11C5/14 ,  G05F1/10

    CPC分类号： G05F3/222 ,  G11C5/147

    摘要： A variable load current supply unit supplies a current to be consumed by a constant voltage output unit to a power source terminal thereof, and supplies a current to be consumed by a load circuit thereto through a reference voltage output terminal. The constant voltage output unit maintains a potential of the power source terminal thereof, i.e., a potential of the reference voltage output terminal, at a fixed potential. A base potential control unit negatively feeds back changes in the potential on the reference voltage output terminal to a base of an emitter follower transistor in the variable load current supply unit. In this way, when the current consumed by the load current is reduced and the potential on the reference voltage output terminal thereby slightly increases the current supplied by the variable load current supply unit decreases.

    摘要翻译： 可变负载电流供给单元将恒定电压输出单元消耗的电流供给到其电源端子，并通过基准电压输出端子向负载电路供给要消耗的电流。 恒定电压输出单元将电源端子的电位即基准电压输出端子的电位维持在固定电位。 基极电位控制单元将可变负载电流供给单元中的基准电压输出端子上的电位的变化负反馈到射极跟随器晶体管的基极。 以这种方式，当负载电流消耗的电流减小并且参考电压输出端子上的电位稍微增加时，可变负载电流供应单元提供的电流减小。

    Level shift circuit
    9.
    发明授权
    Level shift circuit 有权
    电平移位电路

    公开(公告)号：US07639060B2

    公开(公告)日：2009-12-29

    申请号：US12076521

    申请日：2008-03-19

    申请人： Satoshi Shiraki ,  Hiroyuki Ban ,  Junichi Nagata

    发明人： Satoshi Shiraki ,  Hiroyuki Ban ,  Junichi Nagata

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018571 ,  H01L27/0251 ,  H03K5/003 ,  H03K19/00361

    摘要： A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit.

    摘要翻译： 电平移位电路包括：第一电容器电路，包括串联连接在接地和预定电位之间的电容器;耦合到第一电容器电路的预定电位侧的第一触发电路;耦合到第一电容器的接地侧的输入端子 电路，包括串联连接在接地和预定电位之间的电容器的第二电容器电路，耦合到第二电容器电路的预定电位侧的第二触发电路，耦合在第二电容器的输入端子和地电位侧之间的反相器 电容器电路和SR锁存电路，其具有耦合到第一触发电路的输出的第一输入和耦合到第二触发电路的输出的第二输入。