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12 条记录 (耗时 0.031 秒)

    PLASMA PROCESSING APPARATUS
    3.
    发明申请
    PLASMA PROCESSING APPARATUS 有权
    等离子体加工设备

    公开(公告)号：US20070236148A1

    公开(公告)日：2007-10-11

    申请号：US11756097

    申请日：2007-05-31

    申请人： Yohei Yamazawa ,  Manabu Iwata ,  Chishio Koshimizu ,  Fumihiko Higuchi ,  Akitaka Shimizu ,  Asao Yamashita ,  Nobuhiro Iwama ,  Tsutomu Higashiura ,  DongSheng Zhang ,  Michiko Nakaya ,  Norikazu Murakami

    发明人： Yohei Yamazawa ,  Manabu Iwata ,  Chishio Koshimizu ,  Fumihiko Higuchi ,  Akitaka Shimizu ,  Asao Yamashita ,  Nobuhiro Iwama ,  Tsutomu Higashiura ,  DongSheng Zhang ,  Michiko Nakaya ,  Norikazu Murakami

    IPC分类号： H01L21/3065

    CPC分类号： H01J37/32174 ,  H01J37/321

    摘要： An apparatus, which performs a plasma process on a target substrate by using plasma, includes first and second electrodes in a process chamber to oppose each other. An RF field, which turns a process gas into plasma by excitation, is formed between the first and second electrodes. An RF power supply, which supplies RF power, is connected to the first or second electrode through a matching circuit. The matching circuit automatically performs input impedance matching relative to the RF power. A variable impedance setting section is connected to a predetermined member, which is electrically coupled with the plasma, through an interconnection. The impedance setting section sets a backward-direction impedance against an RF component input to the predetermined member from the plasma. A controller supplies a control signal concerning a preset value of the backward-direction impedance to the impedance setting section.

    摘要翻译： 通过使用等离子体在目标基板上进行等离子体处理的装置包括处理室中彼此相对的第一和第二电极。 在第一和第二电极之间形成通过激发将工艺气体转化成等离子体的RF场。 提供RF功率的RF电源通过匹配电路连接到第一或第二电极。 匹配电路自动执行相对于RF功率的输入阻抗匹配。 可变阻抗设定部分通过互连连接到与等离子体电耦合的预定部件。 阻抗设定部分针对从等离子体输入到预定部件的RF分量设置反向阻抗。 控制器将关于反向阻抗的预设值的控制信号提供给阻抗设定部。

    Dry etching method
    4.
    发明授权
    Dry etching method 有权
    干蚀刻法

    公开(公告)号：US07192532B2

    公开(公告)日：2007-03-20

    申请号：US10475268

    申请日：2002-02-27

    申请人： Akiteru Koh ,  Toshihiro Miura ,  Takayuki Fukasawa ,  Akitaka Shimizu ,  Masato Kushibiki ,  Asao Yamashita ,  Fumihiko Higuchi

    发明人： Akiteru Koh ,  Toshihiro Miura ,  Takayuki Fukasawa ,  Akitaka Shimizu ,  Masato Kushibiki ,  Asao Yamashita ,  Fumihiko Higuchi

    IPC分类号： C03C25/68

    CPC分类号： H01J37/32082 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32137

    摘要： A tungsten silicide layer (104) is etched by plasma etching using Cl2+O2 gas as etching gas. When etching of the tungsten silicide layer (104) is ended substantially, etching gas is switched to Cl2+O2+NF3 and over etching is performed by plasma etching. Etching process is ended under a state where a polysilicon layer (103) formed beneath the tungsten silicide layer (104) is slightly etched uniformly. Residual quantity of the polysilicon layer (103) can be made uniform as compared with prior art and a high quality semiconductor device can be fabricated stably.

    摘要翻译： 通过使用Cl 2 O 2 + O 2气体作为蚀刻气体的等离子体蚀刻来蚀刻硅化钨层（104）。 当钨硅化物层（104）的蚀刻基本上结束时，蚀刻气体被切换到Cl 2 + O 2 + N N 3 3并过度 通过等离子体蚀刻进行蚀刻。 在钨硅化物层（104）下方形成的多晶硅层（103）被均匀地微蚀刻的状态下结束蚀刻处理。 与现有技术相比，多晶硅层（103）的剩余量可以均匀，并且可以稳定地制造高质量的半导体器件。

    Dry etching polysilicon using a bromine-containing gas
    6.
    发明授权
    Dry etching polysilicon using a bromine-containing gas 失效
    使用含溴气体干蚀刻多晶硅

    公开(公告)号：US5314573A

    公开(公告)日：1994-05-24

    申请号：US885855

    申请日：1992-05-20

    申请人： Fumihiko Higuchi ,  Yoshio Fukasawa

    发明人： Fumihiko Higuchi ,  Yoshio Fukasawa

    IPC分类号： H01L21/3213 ,  H01L21/306 ,  B44C1/22

    CPC分类号： H01L21/32137

    摘要： The present invention provides a dry etching method for achieving a satisfactory anisotropic etching of, for example, a semiconductor wafer, particularly, a polysilicon layer formed on the wafer. In the present invention, a mixed gas comprising a first gas containing Br and a second gas containing a halogen element other than Br, e.g., a mixed gas consisting of a HBr gas and a HCl gas, is introduced into a vacuum chamber. The mixed gas is converted into plasma by applying a high frequency power to an upper electrode 5. The plasma region is irradiated, as desired, with an ultraviolet light. The semiconductor wafer is etched with the plasma. The etching is carried out under optimum conditions. For example, the surface temperature of the semiconductor wafer, i.e., workpiece, is maintained at a level falling within a range of between 70.degree. C. and 120.degree. C. Also, the flow rate ratio of the mixed gas is suitably controlled.

    摘要翻译： 本发明提供了一种用于实现例如半导体晶片，特别是形成在晶片上的多晶硅层的令人满意的各向异性蚀刻的干蚀刻方法。 在本发明中，将包含Br的第一气体和含有Br以外的卤素元素的第二气体（例如由HBr气体和HCl气体构成的混合气体）的混合气体引入真空室。 通过向上电极5施加高频电力，将混合气体转换为等离子体。根据需要用紫外线照射等离子体区域。 用等离子体蚀刻半导体晶片。 蚀刻在最佳条件下进行。 例如，半导体晶片即工件的表面温度保持在70℃〜120℃的范围内，适当地控制混合气体的流量比。

    Plasma processing apparatus
    7.
    发明授权
    Plasma processing apparatus 有权
    等离子体处理装置

    公开(公告)号：US08251011B2

    公开(公告)日：2012-08-28

    申请号：US11756097

    申请日：2007-05-31

    申请人： Yohei Yamazawa ,  Manabu Iwata ,  Chishio Koshimizu ,  Fumihiko Higuchi ,  Akitaka Shimizu ,  Asao Yamashita ,  Nobuhiro Iwama ,  Tsutomu Higashiura ,  DongSheng Zhang ,  Michiko Nakaya ,  Norikazu Murakami

    发明人： Yohei Yamazawa ,  Manabu Iwata ,  Chishio Koshimizu ,  Fumihiko Higuchi ,  Akitaka Shimizu ,  Asao Yamashita ,  Nobuhiro Iwama ,  Tsutomu Higashiura ,  DongSheng Zhang ,  Michiko Nakaya ,  Norikazu Murakami

    IPC分类号： C23C16/00 ,  C23F1/00 ,  H01L21/306

    CPC分类号： H01J37/32174 ,  H01J37/321

    摘要： An apparatus, which performs a plasma process on a target substrate by using plasma, includes first and second electrodes in a process chamber to oppose each other. An RF field, which turns a process gas into plasma by excitation, is formed between the first and second electrodes. An RF power supply, which supplies RF power, is connected to the first or second electrode through a matching circuit. The matching circuit automatically performs input impedance matching relative to the RF power. A variable impedance setting section is connected to a predetermined member, which is electrically coupled with the plasma, through an interconnection. The impedance setting section sets a backward-direction impedance against an RF component input to the predetermined member from the plasma. A controller supplies a control signal concerning a preset value of the backward-direction impedance to the impedance setting section.

    摘要翻译： 通过使用等离子体在目标基板上进行等离子体处理的装置包括处理室中彼此相对的第一和第二电极。 在第一和第二电极之间形成通过激发将工艺气体转化成等离子体的RF场。 提供RF功率的RF电源通过匹配电路连接到第一或第二电极。 匹配电路自动执行相对于RF功率的输入阻抗匹配。 可变阻抗设定部分通过互连连接到与等离子体电耦合的预定部件。 阻抗设定部分针对从等离子体输入到预定部件的RF分量设置反向阻抗。 控制器将关于反向阻抗的预设值的控制信号提供给阻抗设定部。

    Etching method
    9.
    发明申请
    Etching method 审中-公开
    蚀刻方法

    公开(公告)号：US20050106868A1

    公开(公告)日：2005-05-19

    申请号：US10502853

    申请日：2003-01-31

    申请人： Asao Yamashita ,  Fumihiko Higuchi ,  Takashi Enomoto

    发明人： Asao Yamashita ,  Fumihiko Higuchi ,  Takashi Enomoto

    IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/32137 ,  H01L21/28035

    摘要： An etching method for plasma etching a polysilicon film layer on a gate oxide film formed on a silicon substrate by introducing a processing gas into an airtight processing chamber comprises a main etching step for etching, by applying high frequency powers to the upper and the lower electrode, the polysilicon film in a depth direction of openings of a mask pattern serving as a mask, and an overetching step for removing, after the main etching step, residual parts of the polysilicon film, wherein in the middle of the main etching step, the high frequency power applied to the upper electrode is lowered down to a specific power level or lower, and the polysilicon film is etched until a part of the gate oxide film is exposed. Anisotropy in the profile can be improved while enhancing the selectivity of etching, and total etching rate can be prevented from being lowered.

    摘要翻译： 通过将处理气体引入到气密处理室中，在形成于硅衬底上的栅极氧化膜上等离子体蚀刻多晶硅膜的蚀刻方法包括：通过向上下电极施加高频电力进行蚀刻的主蚀刻步骤 ，作为掩模的掩模图案的开口的深度方向的多晶硅膜，以及用于在主蚀刻步骤之后去除多晶硅膜的剩余部分的过蚀刻步骤，其中在主蚀刻步骤的中间， 施加到上电极的高频功率降低到特定功率水平或更低，并且多晶硅膜被蚀刻直到栅极氧化膜的一部分露出。 可以提高轮廓中的各向异性，同时提高蚀刻的选择性，并且可以防止总的蚀刻速率降低。