公开(公告)号：US07816688B2

公开(公告)日：2010-10-19

申请号：US10494616

申请日：2002-11-27

申请人： Kenya Yamashita ,  Makoto Kitabatake ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Masao Uchida ,  Ryoko Miyanaga

发明人： Kenya Yamashita ,  Makoto Kitabatake ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Masao Uchida ,  Ryoko Miyanaga

IPC分类号： H01L29/51

CPC分类号： H01L21/28185 ,  H01L21/049 ,  H01L21/28202 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7838

摘要： An upper part of a SIC substrate 1 is oxidized at a temperature of 800 to 1400° C., inclusive, in an oxygen atmosphere at 1.4×102 Pa or less, thereby forming a first insulating film 2 which is a thermal oxide film of 20 nm or less in thickness. Thereafter, annealing is performed, and then a first cap layer 3, which is a nitride film of about 5 nm in thickness, is formed thereon by CVD. A second insulating film 4, which is an oxide film of about 130 nm in thickness, is deposited thereon by CVD. A second cap layer 5, which is a nitride film of about 10 nm in thickness, is formed thereon. In this manner, a gate insulating film 6 made of the first insulating film 2 through the second cap layer 5 is formed, thus obtaining a low-loss highly-reliable semiconductor device.

摘要翻译： SIC基板1的上部在氧气气氛中在800〜1400℃的温度下氧化，在1.4×102Pa以下，由此形成作为热氧化膜的第一绝缘膜2 nm以下的厚度。 然后，进行退火，然后通过CVD在其上形成厚度为约5nm的氮化物膜的第一盖层3。 作为厚度约130nm的氧化物膜的第二绝缘膜4通过CVD沉积在其上。 在其上形成厚度为约10nm的氮化膜的第二盖层5。 以这种方式，形成通过第二盖层5由第一绝缘膜2制成的栅极绝缘膜6，从而获得低损耗高可靠性的半导体器件。

公开(公告)号：US07786565B2

公开(公告)日：2010-08-31

申请号：US10536828

申请日：2004-09-06

申请人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

发明人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

IPC分类号： H01L23/492

CPC分类号： H01L23/3735 ,  H01L23/3672 ,  H01L23/4334 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor chip 61, the first and second intermediate member 65 and 68a and the heat conducting member 66. The tips of the base materials 62 and 63 work respectively as external connection terminals 62a and 63a. The second intermediate member 68a is made of a material with lower heat conductivity than the first intermediate member 65, and a contact area with the semiconductor chip 61 is larger in the second intermediate member 68a than in the first intermediate member.

摘要翻译： 半导体装置包括半导体芯片61，其包括使用宽带隙半导体的功率半导体器件，基底材料62和63，第一和第二中间构件65和68a，导热构件66，辐射翅片67和封装材料 用于封装半导体芯片61，第一和第二中间构件65和68a以及导热构件66.基材62和63的顶端分别作为外部连接端子62a和63a工作。 第二中间构件68a由比第一中间构件65低导热性的材料制成，并且与第一中间构件相比，第二中间构件68a的与半导体芯片61的接触面积更大。

公开(公告)号：US06995397B2

公开(公告)日：2006-02-07

申请号：US10466353

申请日：2002-09-17

申请人： Kenya Yamashita ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Masao Uchida ,  Ryoko Miyanaga

发明人： Kenya Yamashita ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Masao Uchida ,  Ryoko Miyanaga

IPC分类号： H01L31/072

CPC分类号： H01L29/66068 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/7828 ,  H01L29/7838

摘要： A semiconductor device having an accumulation channel SiC-MISFET structure includes a p-type SiC layer 10 formed on an SiC substrate, an n-type channel layer 20, a gate insulating film 11, a gate electrode 12, and n-type source and drain layers 13a and 13b. The channel layer 20 includes an undoped layer 22 and a δ doped layer 21 which is formed in the vicinity of the lower end of the undoped layer 22. Since the channel layer 20 includes the high-concentration δ doped layer 21 in its deeper portion, the electric field in the surface region of the channel layer is weakened, thereby allowing the current driving force to increase.

摘要翻译： 具有堆积通道SiC-MISFET结构的半导体器件包括形成在SiC衬底上的p型SiC层10，n型沟道层20，栅极绝缘膜11，栅电极12和n型源， 漏极层13a和13b。 沟道层20包括未掺杂层22和形成在未掺杂层22的下端附近的δ掺杂层21.由于沟道层20在其较深部分包括高浓度δ掺杂层21， 沟道层的表面区域的电场减弱，从而允许电流驱动力增加。

公开(公告)号：US07846828B2

公开(公告)日：2010-12-07

申请号：US12338395

申请日：2008-12-18

申请人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

发明人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/7828 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/30625 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/812

摘要： Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

摘要翻译： 进行离子注入以在SiC衬底上的高电阻SiC层的部分中形成p阱区域和源极区域，并且在衬底上沉积碳膜。 通过沉积在基板上的碳膜，进行用于激活注入的掺杂离子的退火，然后除去碳膜。 因此，获得了退火几乎没有表面粗糙度的光滑表面。 此外，如果沟道层外延生长，则沟道层的表面粗糙度小于下层的表面粗糙度。 由于提供了具有平滑表面的沟道层，所以可以获得具有高电流驱动能力的MISFET。

公开(公告)号：US07462540B2

公开(公告)日：2008-12-09

申请号：US10553845

申请日：2005-01-28

申请人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Kenya Yamashita ,  Masao Uchida ,  Osamu Kusumoto ,  Ryoko Miyanaga

发明人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Kenya Yamashita ,  Masao Uchida ,  Osamu Kusumoto ,  Ryoko Miyanaga

IPC分类号： H01L21/00

CPC分类号： H01L21/046

摘要： A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).

摘要翻译： 一种制造半导体器件的方法包括以下步骤：将离子注入形成在碳化硅衬底（1）上的碳化硅薄膜（2）中，在减压气氛中加热碳化硅衬底以形成碳层（5） 在碳化硅衬底的表面上，并且在比形成碳层（5）的步骤高的压力的气氛中，并且在高于形成步骤的温度的气氛中，相对于碳化硅衬底进行激活退火 碳层（5）。

公开(公告)号：US06995396B2

公开(公告)日：2006-02-07

申请号：US10279119

申请日：2002-10-24

申请人： Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kenya Yamashita ,  Ryoko Miyanaga

发明人： Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kenya Yamashita ,  Ryoko Miyanaga

IPC分类号： H01L31/0312 ,  H01L29/80 ,  H01L31/112 ,  H01L29/76 ,  H01L27/095

CPC分类号： H01L29/365 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/0445 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068

摘要： A SiC bulk substrate whose top face has been flattened is placed in a vertical thin film growth system to be annealed in an inert gas atmosphere. A material gas of Si is then supplied at a flow rate of 1 mL/min. at a substrate temperature of 1200° C. through 1600° C. Subsequently, the diluent gas is changed to a hydrogen gas at a temperature of 1600° C., and material gases of Si and carbon are supplied with nitrogen intermittently supplied, so as to deposit SiC thin films on the SiC bulk substrate. In a flat δ-doped multilayered structure thus formed, an average height of macro steps formed on the top face and on interfaces therein is 30 nm or less. When the resultant substrate is used, a semiconductor device with a high breakdown voltage and high mobility can be realized.

公开(公告)号：US20080265260A1

公开(公告)日：2008-10-30

申请号：US11570269

申请日：2005-06-10

申请人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Koichi Hashimoto

发明人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Koichi Hashimoto

IPC分类号： H01L29/24

CPC分类号： H01L29/7828 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365

摘要： A power device having a transistor structure is formed by using a wide band gap semiconductor. A current path 20 of the power device includes: a JFET (junction) region 2, a drift region 3, and a substrate 4, which have ON resistances exhibiting a positive temperature dependence; and a channel region 1, which has an ON resistance exhibiting a negative temperature dependence. A temperature-induced change in the ON resistance of the entire power device is derived by allowing a temperature-induced change ΔRp in the ON resistance in the JFET (junction) region 2, the drift region 3, and the substrate 4, which have ON resistances exhibiting a positive temperature dependence, and a temperature-induced change ΔRn in the ON resistance in the channel region 1, which has an ON resistance exhibiting a negative temperature dependence, to cancel out each other. With respect to an ON resistance of the entire power device at −30° C., a ratio of change in the ON resistance of the entire power device when a temperature of the power device is varied from −30° C. to 100° C. is 50% or less.

摘要翻译： 通过使用宽带隙半导体形成具有晶体管结构的功率器件。 功率器件的电流通路20包括：具有呈现正温度依赖性的导通电阻的JFET（结）区域2，漂移区域3和衬底4; 以及具有呈现负温度依赖性的导通电阻的沟道区域1。 通过使JFET（结）区域2，漂移区域3中的导通电阻中的温度感应变化ΔR

<！ - SIPO - >于高电平，导致整个功率器件的导通电阻的温度引起的变化， 并且具有呈现正温度依赖性的导通电阻的基板4和沟道区域1中的导通电阻中的温度感应变化ΔR ，其具有呈现负温度依赖性的导通电阻 ，取消对方。 关于整个功率器件在-30℃的导通电阻，当功率器件的温度从-30℃变化到100℃时，整个功率器件的导通电阻的变化率 50％以下。

公开(公告)号：US20070158778A1

公开(公告)日：2007-07-12

申请号：US10588960

申请日：2005-08-26

申请人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Ryoko Miyanaga ,  Koichi Hashimoto

发明人： Makoto Kitabatake ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Ryoko Miyanaga ,  Koichi Hashimoto

IPC分类号： H01L23/58

CPC分类号： H02M7/538 ,  H01L21/8213 ,  H01L21/8252 ,  H01L24/73 ,  H01L27/0605 ,  H01L27/0727 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/14 ,  H02M7/003 ,  H03K17/063 ,  H03K17/6871 ,  Y02B70/1483 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device according to this invention includes: two level shift switches (28A and 28B) each having first and second electrodes, a control electrode, a signal output electrode, and a first semiconductor region forming a transistor device section (28a,28b) which intervenes between the first electrode and the signal output electrode and is brought into or out of conduction according to a signal inputted to the control electrode and a resistor device section (Ra,Rb) which intervenes between the signal output electrode and the second electrode, the first semiconductor region comprising a wide bandgap semiconductor; and a diode (23) having a cathode-side electrode, an anode-side electrode, and a second semiconductor region comprising a wide bandgap semiconductor.

摘要翻译： 根据本发明的半导体器件包括：具有第一和第二电极的两个电平移位开关（28A和28B），控制电极，信号输出电极和形成晶体管器件部分（28a， 28b），其介于所述第一电极和所述信号输出电极之间，并且根据输入到所述控制电极的信号和介于所述信号输出电极和所述信号输出电极之间的电阻器部分（Ra，Rb）而导通或导通; 第二电极，第一半导体区域包括宽带隙半导体; 以及具有阴极侧电极，阳极侧电极和包括宽带隙半导体的第二半导体区域的二极管（23）。

公开(公告)号：US20060220027A1

公开(公告)日：2006-10-05

申请号：US10553845

申请日：2005-01-28

申请人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Kenya Yamashita ,  Masao Uchida ,  Osamu Kusumoto ,  Ryoko Miyanaga

发明人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Kenya Yamashita ,  Masao Uchida ,  Osamu Kusumoto ,  Ryoko Miyanaga

IPC分类号： H01L31/0312 ,  H01L21/265

CPC分类号： H01L21/046

摘要： A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).

摘要翻译： 一种制造半导体器件的方法包括以下步骤：将离子注入形成在碳化硅衬底（1）上的碳化硅薄膜（2）中，在减压气氛中加热碳化硅衬底以形成碳层（5） 在碳化硅衬底的表面上，并且在比形成碳层（5）的步骤高的压力的气氛中，并且在高于形成步骤的温度的气氛中，相对于碳化硅衬底进行激活退火 碳层（5）。

公开(公告)号：US20050173739A1

公开(公告)日：2005-08-11

申请号：US10494705

申请日：2003-07-09

申请人： Osamu Kusumoto ,  Makoto Kitabatake ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Ryoko Miyanaga ,  Masao Uchida

发明人： Osamu Kusumoto ,  Makoto Kitabatake ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Ryoko Miyanaga ,  Masao Uchida

IPC分类号： H01L21/28 ,  H01L21/04 ,  H01L21/336 ,  H01L21/338 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8232 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/095 ,  H01L29/12 ,  H01L29/24 ,  H01L29/36 ,  H01L29/45 ,  H01L29/47 ,  H01L29/772 ,  H01L29/78 ,  H01L29/812 ,  H01L29/872 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/7813 ,  H01L21/0485 ,  H01L21/8213 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7725 ,  H01L29/7828 ,  H01L29/7838 ,  H01L29/812 ,  H01L29/872 ,  Y10S438/931

摘要： An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple δ-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and δ-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.

摘要翻译： 累积模式MISFET包括：在SiC衬底101上外延生长的高电阻SiC层102; 井区域103; 具有形成在阱区域103的表面区域上的多个δ-掺杂层的累积沟道层104; 接触区域105; 栅极绝缘膜108; 和栅电极110。 累积通道层104具有这样的结构，其中未掺杂层104b和δ-掺杂层104a允许载流子在量子效应下向未掺杂层104b的扩展移动交替堆叠。 提供源电极111，其进入累积沟道层104和接触区域105以与接触区域105直接接触。 不需要通过离子注入形成源极区域，导致制造成本的降低。