公开(公告)号：US20100117135A1

公开(公告)日：2010-05-13

申请号：US12564349

申请日：2009-09-22

申请人： Makoto MIZUKAMI ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

发明人： Makoto MIZUKAMI ,  Kiyohito Nishihara ,  Masaki Kondo ,  Takashi Izumida ,  Hirokazu Ishida ,  Atsushi Fukumoto ,  Fumiki Aiso ,  Daigo Ichinose ,  Tadashi Iguchi

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer.

摘要翻译： 半导体器件形成在具有半导体衬底的SOI衬底上，形成在半导体衬底上的掩埋氧化膜以及形成在掩埋氧化膜上的半导体层，该半导体衬底具有第一导电类型，该半导体层具有第二导电型 导电型，其中所述掩埋氧化物膜具有通过其开口的第一开口，用于使所述半导体衬底与所述半导体层连通，所述半导体层被布置为具有埋在所述第一开口中的与所述半导体衬底接触的第一掩埋部分和半导体层 主要部分位于第一掩埋部分和掩埋氧化膜上，半导体衬底具有埋在半导体衬底的表面中并与第一开口中的第一掩埋部分电连接的连接层，连接层具有第二导电 类型，并且半导体器件包括接触电极 阴极埋入第二开口中，接触电极的侧表面连接到半导体层主体部分，接触电极的底表面连接到连接层，第二开口穿过半导体层主体部分和埋设 氧化膜，第二开口到达连接层的表面部分。

公开(公告)号：US20100140213A1

公开(公告)日：2010-06-10

申请号：US12618039

申请日：2009-11-13

申请人： Makoto MIZUKAMI ,  Kiyohito NISHIHARA

发明人： Makoto MIZUKAMI ,  Kiyohito NISHIHARA

IPC分类号： B44C1/22 ,  B05D3/00 ,  B03C1/00

CPC分类号： B03C1/08 ,  B03C1/24 ,  B03C2201/20 ,  B03C2201/26 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/172 ,  C01B2202/22

摘要： An apparatus for manufacturing carbon nano tubes of an aspect of the present invention including an introducing unit commonly introducing a first carbon nano tube having first magnetic characteristics and a second carbon nano tube having second magnetic characteristics different from the first magnetic characteristics, first and second collecting units collecting the first and second carbon nano tubes, respectively, a transport unit transporting the first and second carbon nano tubes from the introducing unit to the first and second collecting units, and at least one of a magnetic field generating unit which is provided adjacent to the transport unit and applies a magnetic field to the first and second carbon nano tubes, wherein the first carbon nano tube and the second carbon nano tube are sorted by the magnetic field generating unit.

摘要翻译： 本发明的一个方面的碳纳米管的制造装置，其特征在于，包括通常导入具有第一磁特性的第一碳纳米管的导入部和具有与第一磁特性不同的第二磁特性的第二碳纳米管，第一和第二收集 分别收集第一和第二碳纳米管的传送单元，其将第一和第二碳纳米管从引入单元传送到第一和第二收集单元;以及至少一个磁场产生单元， 所述输送单元对所述第一和第二碳纳米管施加磁场，其中所述第一碳纳米管和所述第二碳纳米管由所述磁场产生单元分选。

公开(公告)号：US20070138576A1

公开(公告)日：2007-06-21

申请号：US11608393

申请日：2006-12-08

申请人： Makoto MIZUKAMI ,  Fumitaka ARAI

发明人： Makoto MIZUKAMI ,  Fumitaka ARAI

IPC分类号： H01L29/76 ,  H01L21/82

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.

摘要翻译： 具有多个存储单元晶体管的线性排列的非易失性半导体存储器包括：具有第一导电类型的第一半导体层; 第二半导体层，设置在所述第一半导体层上以防止杂质从所述第一半导体层扩散到所述第二半导体层上方的区域; 以及设置在所述第二半导体层上的第三半导体层，包括具有第二导电类型的第一源极区域，具有第二导电类型的第一漏极区域和具有用于每个存储单元晶体管的第二导电类型的第一沟道区域。

公开(公告)号：US20090008650A1

公开(公告)日：2009-01-08

申请号：US12182816

申请日：2008-07-30

申请人： Makoto MIZUKAMI ,  Takashi Shinohe

发明人： Makoto MIZUKAMI ,  Takashi Shinohe

IPC分类号： H01L29/24

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/7392 ,  H01L29/7828 ,  H01L29/8083

摘要： A decrease in breakdown voltage can be prevented as much as possible. A field-effect transistor includes: a drain region made of SiC; a drift layer which is formed on the drain region and is made of n-type SiC; a source region which is formed on the surface of the drift layer and is made of n-type SiC; a channel region which is formed on the surface of the drift layer located on a side of the source region and is made of SiC; an insulating gate which is formed on the channel region; and a p-type base region interposed between the bottom portion of the source region and the drift region, and containing two kinds of p-type impurities.

摘要翻译： 可以尽可能地防止击穿电压的降低。 场效应晶体管包括：由SiC制成的漏区; 漂移层，其形成在漏区，由n型SiC制成; 源区，其形成在漂移层的表面上并由n型SiC制成; 沟道区，形成在位于源极区一侧的漂移层的表面上并由SiC制成; 形成在沟道区上的绝缘栅; 以及插入在源极区域的底部与漂移区域之间的p型基极区域，并且含有两种p型杂质。

公开(公告)号：US20120228635A1

公开(公告)日：2012-09-13

申请号：US13409820

申请日：2012-03-01

申请人： Makoto MIZUKAMI ,  Masamu Kamaga ,  Kazuto Takao

发明人： Makoto MIZUKAMI ,  Masamu Kamaga ,  Kazuto Takao

IPC分类号： H01L29/161

CPC分类号： H01L29/868 ,  H01L29/1608

摘要： A semiconductor rectifier device using an SiC semiconductor at least includes: an anode electrode; an anode area that adjoins the anode electrode and is made of a second conductivity type semiconductor; a drift layer that adjoins the anode area and is made of a first conductivity type semiconductor having a low concentration; a minority carrier absorption layer that adjoins the drift layer and is made of a first conductivity type semiconductor having a higher concentration than that of the drift layer; a high-resistance semiconductor area that adjoins the minority carrier absorption layer, has less thickness than the drift layer and is made of a first conductivity type semiconductor having a concentration lower than that of the minority carrier absorption layer; a cathode contact layer that adjoins the semiconductor area; and a cathode electrode.

摘要翻译： 使用SiC半导体的半导体整流装置至少包括：阳极电极; 邻接阳极电极并由第二导电型半导体制成的阳极区域; 漂移层，其邻接阳极区域并由具有低浓度的第一导电型半导体制成; 与漂移层相邻并且由比漂移层的浓度高的第一导电型半导体制成的少数载流子吸收层; 与少数载流子吸收层相邻的高电阻半导体区域的厚度小于漂移层的厚度，并且由具有低于少数载流子吸收层的浓度的第一导电型半导体构成; 邻接半导体区域的阴极接触层; 和阴极电极。

公开(公告)号：US20110175106A1

公开(公告)日：2011-07-21

申请号：US12716386

申请日：2010-03-03

申请人： Makoto MIZUKAMI ,  Takashi Shinohe ,  Johji Nishio

发明人： Makoto MIZUKAMI ,  Takashi Shinohe ,  Johji Nishio

IPC分类号： H01L29/24

CPC分类号： H01L29/1608 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/45 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor rectifier includes: a wide bandgap semiconductor substrate of a first conductivity type; a wide bandgap semiconductor layer of the first conductivity type which is formed on an upper surface of the wide bandgap semiconductor substrate and has an impurity concentration of 1E+14 atoms/cm3 or more and 5E+16 atoms/cm3 or less and a thickness of 20 μm or more; a first wide bandgap semiconductor region of the first conductivity type formed on a surface of the wide bandgap semiconductor layer; a second wide bandgap semiconductor region of a second conductivity type formed to be sandwiched by the first wide bandgap semiconductor regions; a first electrode formed on the first and second wide bandgap semiconductor regions; and a second electrode formed on a lower surface of the wide bandgap semiconductor substrate, wherein a width of the second wide bandgap semiconductor region is 15 μm or more.

摘要翻译： 半导体整流器包括：第一导电类型的宽带隙半导体衬底; 第一导电类型的宽带隙半导体层形成在宽带隙半导体衬底的上表面上，杂质浓度为1E + 14原子/厘米3以上且5E + 16原子/ cm 3以下，厚度为 20μm以上; 形成在宽带隙半导体层的表面上的第一导电类型的第一宽带隙半导体区域; 形成为被第一宽带隙半导体区域夹持的第二导电类型的第二宽带隙半导体区域; 形成在所述第一宽带隙半导体区域和所述第二宽带隙半导体区域上的第一电极; 以及形成在宽带隙半导体衬底的下表面上的第二电极，其中第二宽带隙半导体区域的宽度为15μm以上。

公开(公告)号：US20110085377A1

公开(公告)日：2011-04-14

申请号：US12974128

申请日：2010-12-21

申请人： Makoto MIZUKAMI ,  Fumitaka Arai

发明人： Makoto MIZUKAMI ,  Fumitaka Arai

IPC分类号： G11C11/35 ,  H01L21/28

CPC分类号： H01L27/11578 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

摘要翻译： 根据本发明的一个方面，提供一种非易失性半导体存储装置，包括：基板; 堆叠部分，其包括多个导体层和交替堆叠在所述基板上的多个绝缘层，所述多个导体层中的至少一层和所述多个绝缘层形成标记层; 电荷累积膜，其形成在从其顶表面到底表面形成在堆叠部分中的存储器插塞孔的内表面上; 以及通过电荷累积膜形成在存储器插塞孔内部的半导体柱。

公开(公告)号：US20110065272A1

公开(公告)日：2011-03-17

申请号：US12948412

申请日：2010-11-17

申请人： Makoto MIZUKAMI ,  Takeshi Kamigaichi

发明人： Makoto MIZUKAMI ,  Takeshi Kamigaichi

IPC分类号： H01L21/768 ,  B32B38/04

CPC分类号： H01L23/5283 ,  H01L21/0217 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/06 ,  H01L2924/0002 ,  Y10T156/1057 ,  H01L2924/00

摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

摘要翻译： 根据本发明实施例的叠层多层结构包括：堆叠层部分，包括多个导电层和多个绝缘层，所述多个绝缘层与所述多个导电层的每个层交替叠层，一个 所述多个绝缘层是所述多个导电层和所述多个绝缘层中的最上层; 和多个触点，所述多个触点的每个触点由所述最顶层形成，并且所述多个触点的每个触点与所述多个导电层的相应导电层接触，所述多个触点的每一个的侧表面 的触点经由绝缘膜与所述多个导电层绝缘。

公开(公告)号：US20090011559A1

公开(公告)日：2009-01-08

申请号：US12206762

申请日：2008-09-09

申请人： Makoto MIZUKAMI ,  Fumitaka ARAI

发明人： Makoto MIZUKAMI ,  Fumitaka ARAI

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.

摘要翻译： 具有多个存储单元晶体管的线性排列的非易失性半导体存储器包括：具有第一导电类型的第一半导体层; 第二半导体层，设置在所述第一半导体层上以防止杂质从所述第一半导体层扩散到所述第二半导体层上方的区域; 以及设置在所述第二半导体层上的第三半导体层，包括具有第二导电类型的第一源极区域，具有第二导电类型的第一漏极区域和具有用于每个存储单元晶体管的第二导电类型的第一沟道区域。