公开(公告)号：US5289517A

公开(公告)日：1994-02-22

申请号：US757139

申请日：1991-09-10

申请人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Sanshiro Obara

发明人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Sanshiro Obara

IPC分类号： G01P3/489 ,  H02P29/00 ,  H03L7/00

CPC分类号： G01P3/489

摘要： A digital pulse processing device is capable of selecting desired precision. The digital pulse processing device includes a counter group for counting pulses output from a pulse output device, the counter group having a plurality of counters A and B that can be separated from and coupled with each other, a mode control circuit for instructing separation and coupling of the counters A and B, and a control circuit for separating and coupling the counters A and B in accordance with the instruction of the mode control circuit. An overflow condition of the free-run counter B is detected using an overflow flag. Detection of an overflow is conducted by setting the flag when an overflow condition has occurred twice or more. The flag is reset by rewriting the state of the flag by a software. An overflow condition which has occurred for the first time is detected in the conventional manner and is treated as carry or borrow. A register is provided to hold the value of the counter B when a microcomputer reads in the counter B. In this way, even when .DELTA.A(i)=0, speed detection operation can be executed using the value of the counter B obtained synchronously with the counting of the counter A.

摘要翻译： 数字脉冲处理装置能够选择期望的精度。 数字脉冲处理装置包括用于对从脉冲输出装置输出的脉冲进行计数的计数器组，该计数器组具有可以彼此分离和耦合的多个计数器A和B，用于指示分离和耦合的模式控制电路 计数器A和B的控制电路，以及根据模式控制电路的指令分离和耦合计数器A和B的控制电路。 使用溢出标志来检测自由运行计数器B的溢出状态。 当溢出条件发生两次以上时，通过设置标志来进行溢出检测。 通过用软件重写标志的状态来重置该标志。 以常规方式检测出第一次发生的溢出状况，并作为进位或借位处理。 当微计算机读入计数器B时，提供寄存器来保持计数器B的值。这样，即使当（Δ）A（i）= 0时，也可以使用计数器B的值来执行速度检测操作 与计数器A的计数同步获得。

公开(公告)号：US5771047A

公开(公告)日：1998-06-23

申请号：US355517

申请日：1994-12-14

申请人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Koyo Katsura

发明人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Koyo Katsura

IPC分类号： G06T11/20 ,  G06T11/00

CPC分类号： G06T11/203

摘要： To reduce the hardware of the graphics computer in size and reduce the cost of the hardware, the frame buffer and the main memory are united into one unit to process graphics data in the CPU. The frame buffer is arranged in the main memory, and the graphics computer includes a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device, such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer. Especially, the said memories are formed so that a single function procedure and a multifunction procedure can be selected to suit the drawing object. In addition, the single function procedure includes a line drawing procedure that uses data tables and a multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one unit, the CPU can be used to process graphics data. Thus, the graphics computer hardware is reduced in size and the cost of the hardware is reduced.

摘要翻译： 为了减小图形计算机的硬件尺寸并降低硬件成本，将帧缓冲器和主存储器联合成一个单元来处理CPU中的图形数据。 帧缓冲器布置在主存储器中，并且图形计算机包括用于从帧缓冲器读取像素数据以进行显示的DMAC，用于接收像素数据并将其显示在诸如LCD的显示设备上的显示器， 以及用于存储CPU使用的程序来绘制所述帧缓冲器中的像素数据的存储器。 特别地，所述存储器被形成为使得可以选择单个功能过程和多功能过程以适合绘图对象。 另外，单功能过程包括使用数据表的线条画过程和使用模式表和掩码表的多值扩展过程。 由于帧缓冲器和主存储器被组合成一个单元，所以CPU可以用于处理图形数据。 因此，图形计算机硬件的尺寸减小，硬件的成本降低。

公开(公告)号：US06677950B1

公开(公告)日：2004-01-13

申请号：US08996151

申请日：1997-12-22

申请人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Koyo Katsura

发明人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Koyo Katsura

IPC分类号： G06T1500

CPC分类号： G06T11/203

摘要： To reduce the hardware of the graphics computer in size and reduce the cost of the hardware, the frame buffer and the main memory are united into one unit to process graphics data in the CPU. The frame buffer is arranged in the main memory, and the graphics computer includes a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device, such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer. Especially, the said memories are formed so that a single function procedure and 2 multifunction procedure can be selected to suit the drawing object. In addition, the single function procedure includes 2 line drawing procedure that uses data tables and 2 multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one unit, the CPU can be used to process graphics data. Thus, the graphics computer hardware is reduced in size and the cost of the hardware is reduced.

摘要翻译： 为了减小图形计算机的硬件尺寸并降低硬件成本，将帧缓冲器和主存储器联合成一个单元来处理CPU中的图形数据。 帧缓冲器布置在主存储器中，并且图形计算机包括用于从帧缓冲器读取像素数据以进行显示的DMAC，用于接收像素数据并将其显示在诸如LCD的显示设备上的显示器， 以及用于存储CPU使用的程序来绘制所述帧缓冲器中的像素数据的存储器。 特别地，所述存储器被形成为使得可以选择单个功能过程和2多功能过程以适合绘图对象。 另外，单功能过程包括使用数据表的2行绘图过程和使用模式表和掩码表的2多值扩展过程。 由于帧缓冲器和主存储器被组合成一个单元，所以CPU可以用于处理图形数据。 因此，图形计算机硬件的尺寸减小，硬件的成本降低。

公开(公告)号：US5504912A

公开(公告)日：1996-04-02

申请号：US830460

申请日：1992-02-05

申请人： Shigeki Morinaga ,  Norio Nakagawa ,  Mitsuru Watabe ,  Mamoru Ohba ,  Hiroyuki Kida ,  Hisashi Kaziwara ,  Takeshi Asai ,  Junichi Tatezaki

发明人： Shigeki Morinaga ,  Norio Nakagawa ,  Mitsuru Watabe ,  Mamoru Ohba ,  Hiroyuki Kida ,  Hisashi Kaziwara ,  Takeshi Asai ,  Junichi Tatezaki

IPC分类号： G06F7/00 ,  G06F9/38 ,  G06F15/16 ,  G06F15/167

CPC分类号： G06F9/3877 ,  G06F9/3885

摘要： The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.

摘要翻译： 协处理器的接口部分设置有FIFO（先进先出）缓冲器和用于连续接受指令的装置。 指令的流水线控制可以以这种方式进行，并且还提供了与微处理器相关联的协议装置。

公开(公告)号：US5642499A

公开(公告)日：1997-06-24

申请号：US223834

申请日：1994-04-06

申请人： Mamoru Ohba ,  Shigeki Morinaga ,  Mitsuru Watabe ,  Hiroyuki Kida

发明人： Mamoru Ohba ,  Shigeki Morinaga ,  Mitsuru Watabe ,  Hiroyuki Kida

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F11/28 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F9/461 ,  G06F9/30025 ,  G06F9/3861 ,  G06F9/3885

摘要： In a coprocessor system having a central processing unit (CPU), a floating-point processing unit (FPU) and a memory (RAM), coupled with each other through buses, when the CPU issues a save command to the FPU, the FPU discriminates the attribute, i.e., a long command or a short command, of a current command executed by the FPU upon receipt of the save command and the internal status thereof. In response to the discrimination result, the FPU interrupts the execution of the current command at once to start the execution of the received save command, when the current command is a long command, and the FPU executes the received save command after the completion of execution of the current command, if the current command is a short command. The attribute of a command is determined in advance on the basis of a time necessary for executing the command and a predetermined criterion provided therefor.

摘要翻译： 在具有中央处理单元（CPU）的协处理器系统中，当CPU向FPU发出保存命令时，通过总线彼此耦合的浮点处理单元（FPU）和存储器（RAM），FPU鉴别 FPU在接收到保存命令及其内部状态时执行的当前命令的属性，即长命令或短命令。 响应于鉴别结果，FPU一旦中断当前命令的执行，开始执行接收到的保存命令，当前命令为长命令，并且FPU在执行完成后执行接收到的保存命令 的当前命令，如果当前命令是一个短命令。 基于执行命令所需的时间和为此提供的预定标准，预先确定命令的属性。