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    MODULAR INTEGRATED CIRCUIT WITH UNIFORM ADDRESS MAPPING
    3.
    发明申请
    MODULAR INTEGRATED CIRCUIT WITH UNIFORM ADDRESS MAPPING 有权
    具有均匀地址映射的模块化集成电路

    公开(公告)号：US20110264930A1

    公开(公告)日：2011-10-27

    申请号：US12767208

    申请日：2010-04-26

    申请人： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    发明人： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    IPC分类号： G06F12/06 ,  G06F1/04 ,  G06F1/26

    CPC分类号： G06F9/00 ,  G06F1/06 ,  G06F1/189 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

    摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.

    摘要翻译： 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件根据存储器映射进行操作，存储器映射包括与为多个辐条模块保留的存储器相对应的多个第一保留块，以及对应于至少一个可选辐条模块保留的存储器的至少一个第二保留块。 基于配置数据激活多个第一保留块，并且基于配置数据停用至少一个第二保留块。

    Modular integrated circuit with uniform address mapping
    4.
    发明授权
    Modular integrated circuit with uniform address mapping 有权
    具有统一地址映射的模块化集成电路

    公开(公告)号：US08417930B2

    公开(公告)日：2013-04-09

    申请号：US12767208

    申请日：2010-04-26

    申请人： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    发明人： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    IPC分类号： G06F9/00 ,  G06F9/24 ,  G06F15/177

    CPC分类号： G06F9/00 ,  G06F1/06 ,  G06F1/189 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

    摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.

    摘要翻译： 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件根据存储器映射进行操作，存储器映射包括与为多个辐条模块保留的存储器相对应的多个第一保留块，以及对应于至少一个可选辐条模块保留的存储器的至少一个第二保留块。 基于配置数据激活多个第一保留块，并且基于配置数据停用至少一个第二保留块。

    Modular integrated circuit with common software
    5.
    发明授权
    Modular integrated circuit with common software 有权
    具有通用软件的模块化集成电路

    公开(公告)号：US08392696B2

    公开(公告)日：2013-03-05

    申请号：US12767201

    申请日：2010-04-26

    申请人： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    发明人： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    IPC分类号： G06F9/24 ,  G06F15/177

    CPC分类号： G06F1/3296 ,  G06F1/266 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

    摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The spoke modules include a plurality of interface circuits each having a hardware address. A memory module stores the hub software and hub data and configuration data. The hub software includes a plurality of driver modules corresponding to the plurality of interface circuits. The processing module executes boot firmware to configure the plurality of driver modules based on the hardware address of each of the plurality of interface circuits.

    摘要翻译： 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 辐条模块包括多个具有硬件地址的接口电路。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件包括对应于多个接口电路的多个驱动器模块。 处理模块基于多个接口电路中的每一个的硬件地址执行引导固件以配置多个驱动器模块。

    MODULAR INTEGRATED CIRCUIT WITH UNIFORM ADDRESS MAPPING
    6.
    发明申请
    MODULAR INTEGRATED CIRCUIT WITH UNIFORM ADDRESS MAPPING 审中-公开
    具有均匀地址映射的模块化集成电路

    公开(公告)号：US20130138936A1

    公开(公告)日：2013-05-30

    申请号：US13752961

    申请日：2013-01-29

    申请人： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    发明人： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    IPC分类号： G06F9/00

    CPC分类号： G06F9/00 ,  G06F1/06 ,  G06F1/189 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

    摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.

    摘要翻译： 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件根据存储器映射进行操作，存储器映射包括与为多个辐条模块保留的存储器相对应的多个第一保留块，以及对应于至少一个可选辐条模块保留的存储器的至少一个第二保留块。 基于配置数据激活多个第一保留块，并且基于配置数据停用至少一个第二保留块。

    MODULAR INTEGRATED CIRCUIT WITH COMMON SOFTWARE
    7.
    发明申请
    MODULAR INTEGRATED CIRCUIT WITH COMMON SOFTWARE 有权
    具有通用软件的模块化集成电路

    公开(公告)号：US20110264901A1

    公开(公告)日：2011-10-27

    申请号：US12767201

    申请日：2010-04-26

    申请人： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    发明人： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

    IPC分类号： G06F15/177 ,  G06F1/04 ,  G06F1/24 ,  G06F12/02

    CPC分类号： G06F1/3296 ,  G06F1/266 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

    摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The spoke modules include a plurality of interface circuits each having a hardware address. A memory module stores the hub software and hub data and configuration data. The hub software includes a plurality of driver modules corresponding to the plurality of interface circuits. The processing module executes boot firmware to configure the plurality of driver modules based on the hardware address of each of the plurality of interface circuits.

    摘要翻译： 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 辐条模块包括多个具有硬件地址的接口电路。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件包括对应于多个接口电路的多个驱动器模块。 处理模块基于多个接口电路中的每一个的硬件地址执行引导固件以配置多个驱动器模块。

    Method and system for advance high performance bus synchronizer
    8.
    发明授权
    Method and system for advance high performance bus synchronizer 有权
    先进高性能总线同步器的方法和系统

    公开(公告)号：US08989331B2

    公开(公告)日：2015-03-24

    申请号：US11806397

    申请日：2007-05-31

    申请人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar, III ,  Vafa J. Rakshani

    发明人： Sam H. Liu ,  Zhiqing Zhuang ,  Chaoyang Zhao ,  Vinay Bhasin ,  Chenmin Zhang ,  Lawrence J. Madar, III ,  Vafa J. Rakshani

    IPC分类号： H04L7/00 ,  H04L7/02 ,  G06F1/12

    CPC分类号： H04L7/02 ,  G06F1/12 ,  H04L7/0012

    摘要： Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

    摘要翻译： 提供了一种用于将数据从同步器内的一个时钟域传送到同步器内的另一个域的方法。 该方法包括确定同步器内的系统时钟参数，并基于系统时钟参数分析第一域时钟信号。 接下来，基于第一域时钟信号和系统时钟参数来分析第二域时钟信号。 根据第一和第二域时钟信号的分析，确定何时将数据从第一时钟域传送到第二时钟域，并且提供使能信号以影响从第一域到第 第二个时钟域。

    Reconfigurable processing system and method
    9.
    发明授权
    Reconfigurable processing system and method 有权
    可重构的处理系统和方法

    公开(公告)号：US06959378B2

    公开(公告)日：2005-10-25

    申请号：US10004246

    申请日：2001-11-02

    申请人： John R. Nickolls ,  Scott D. Johnson ,  Mark Williams ,  Ethan Mirsky ,  Kambdur Kirthiranjan ,  Amrit Raj Pant ,  Lawrence J. Madar, III

    发明人： John R. Nickolls ,  Scott D. Johnson ,  Mark Williams ,  Ethan Mirsky ,  Kambdur Kirthiranjan ,  Amrit Raj Pant ,  Lawrence J. Madar, III

    IPC分类号： G06F9/302 ,  G06F9/318 ,  G06F9/32 ,  G06F9/345 ,  G06F15/78 ,  G06F9/30 ,  G06F19/00

    CPC分类号： G06F9/3001 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/345 ,  G06F9/3455 ,  G06F15/8061

    摘要： A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed. For each vector, vector address units provide addresses which stride through each element of each vector.

    摘要翻译： 可重构处理系统并行执行指令和配置。 最初，第一条指令将配置加载到配置寄存器中。 随后取出的指令的配置字段选择配置寄存器。 所选配置寄存器中的配置的指令控制和控制按照指令进行解码和修改。 控件向处理操作数并生成结果的执行单元提供数据操作数。 可以处理标量数据，向量数据或标量和向量数据的组合。 处理由与指令中的配置字段调用的配置并行执行的指令控制。 使用存储向量的向量寄存器文件处理向量。 向量地址单元标识要处理的向量寄存器文件中的向量元素的地址。 对于每个向量，向量地址单元提供跨越每个向量的每个元素的地址。

    Apparatus and method for providing hardware security
    10.
    发明授权
    Apparatus and method for providing hardware security 有权
    提供硬件安全性的装置和方法

    公开(公告)号：US08826039B2

    公开(公告)日：2014-09-02

    申请号：US12714383

    申请日：2010-02-26

    申请人： Paul Chou ,  Love Kothari ,  Lawrence J. Madar, III

    发明人： Paul Chou ,  Love Kothari ,  Lawrence J. Madar, III

    IPC分类号： G06F12/14

    CPC分类号： G06F21/72 ,  G06F12/14

    摘要： A technique to provide a hardware security module that provides a secure boundary for retention of a secure key within the secure boundary and prevention of unauthorized accesses from external sources outside of the secure boundary to obtain the secure key. The hardware security module includes a security processor to unwrap and authenticate a secure key within the secure boundary to decrypt or encrypt data and to provide data through a single interface that communicates with external sources, so that all data transfers between the secure boundary, formed by the hardware security module, and external sources are transferred only through the interface. The hardware security module ensures no unwrapped key leaves the secure boundary established by the hardware security module.

    摘要翻译： 一种提供硬件安全模块的技术，其提供用于将安全密钥保持在安全边界内的安全边界，并防止从安全边界外部的外部源的未经授权的访问以获得安全密钥。 硬件安全模块包括一个安全处理器，用于对安全边界内的安全密钥进行解包和认证，以对数据进行解密或加密，并通过与外部源通信的单一接口提供数据，从而在安全边界之间传输所有数据，由 硬件安全模块和外部源仅通过接口传输。 硬件安全模块确保没有解开的密钥离开硬件安全模块建立的安全边界。