公开(公告)号：US20090063717A1

公开(公告)日：2009-03-05

申请号：US11846066

申请日：2007-08-28

Applicant: Mark R. Bohm ,  Morgan H. Monks ,  Henry Wurzburg

Inventor： Mark R. Bohm ,  Morgan H. Monks ,  Henry Wurzburg

IPC: G06F3/00

CPC classification number: G06F13/4045 ,  G06F2213/0042

Abstract: A USB communications interface (USBCI) may enable communication between a high-speed USB device, e.g. a High-Speed-Inter-Chip (HSIC) USB device, and a non high-speed USB host, e.g. a full-speed USB host. The USBCI may receive first data from the USB host via a non high-speed transaction, and buffer the first data. The USBCI may also initiate a high-speed transaction corresponding to the non high-speed transaction to the USB device, and transmit at least a portion of the buffered first data to the USB device via the high-speed transaction. The USBCI may subsequently receive second data from the USB device via the high-speed transaction, and buffer the second data. The USBCI may also transmit at least a portion of the buffered second data to the USB host via the non high-speed transaction, and complete the non high-speed transaction upon the high-speed transaction completing.

Abstract translation: USB通信接口（USBCI）可以实现高速USB设备之间的通信，例如， 高速片上（HSIC）USB设备和非高速USB主机，例如， 全速USB主机。 USBCI可以通过非高速事务从USB主机接收第一个数据，并缓冲第一个数据。 USBCI还可以向USB设备发起与非高速交易相对应的高速交易，并且经由高速交易将缓冲的第一数据的至少一部分发送到USB设备。 USBCI可以随后经由高速事务从USB设备接收第二数据，并缓冲第二数据。 USBCI还可以经由非高速事务将缓冲的第二数据的至少一部分传送到USB主机，并且在高速交易完成时完成非高速交易。

公开(公告)号：US20080126594A1

公开(公告)日：2008-05-29

申请号：US11465195

申请日：2006-08-17

Applicant: Morgan H. Monks ,  Mark R. Bohm

Inventor： Morgan H. Monks ,  Mark R. Bohm

IPC: G06F3/00

CPC classification number: G06F1/266

Abstract: System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.

Abstract translation: 用于枚举和/或枚举设备的系统和方法。 该设备可以是遵守第一标准（例如USB规范）的USB便携式设备，并且可以参照关于USB集线器/ USB主机设备的枚举。 在设备中包括的电池足够低的情况下，该设备可以从事低功率枚举，例如开始使用枚举功率对设备充电。 低功耗枚举可能允许设备枚举，即使设备无法启动。 另外或替代地，设备可以确定集线器/主设备是否能够提供高功率充电。 如果是，则设备可以使用由集线器/主机设备提供的功率以高功率电平开始对设备的电池充电。

公开(公告)号：US20070245057A1

公开(公告)日：2007-10-18

申请号：US11425613

申请日：2006-06-21

Applicant: Mark R. Bohm ,  Atish Ghosh

Inventor： Mark R. Bohm ,  Atish Ghosh

IPC: G06F13/20

CPC classification number: G06F13/385

Abstract: A shared USB device may be simultaneously configured and accessed by two or more USB hosts by using a multi-host capable device controller. The multi-host capable device may include separate upstream ports and buffers for each host, and may be configured with the capability to respond to USB requests from more than one host. The multi-host capable device may maintain a dedicated address, configuration, and response information for each host. Each host may therefore establish a dedicated USB connection with the sharing device without the sharing device having to be re-configured or re-enumerated each and every time the upstream hosts alternate accessing the USB device.

Abstract translation: 可以通过使用具有多主机功能的设备控制器由两个或多个USB主机同时配置和访问共享的USB设备。 具有多主机功能的设备可以包括用于每个主机的单独的上行端口和缓冲器，并且可以被配置为具有响应来自多于一个主机的USB请求的能力。 支持多主机的设备可以维护每个主机的专用地址，配置和响应信息。 因此，每个主机可以与共享设备建立专用的USB连接，而不需要每次上游主机交替访问USB设备时重新配置或重新枚举共享设备。

公开(公告)号：US20120137032A1

公开(公告)日：2012-05-31

申请号：US13246365

申请日：2011-09-27

Applicant: Mark R. Bohm

Inventor： Mark R. Bohm

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F1/3203 ,  G06F1/3253 ,  G06F2213/0042 ,  Y02D10/151

Abstract: A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract translation: 简单的数据传输机制可以与静态总线信号组合，以用数字串行互连总线（DSIB）代替USB。 这可以消除USB中所需的各种上拉/下拉电阻，并且当总线处于空闲状态或数据传输状态时，使DSIB能够很少或没有泄漏电流工作。 所有必需的功能可以仅使用两个信号引脚来实现。 DSIB还可以为不需要PLL的高速USB启用硅解决方案，因为时钟可能由传输源提供，因此可能不需要从串行数据流中恢复。 DSIB可以通过使设计人员能够移除模拟PHY并用串行数字I / O传输机制替代它，同时保留IP的USB定时器以及其他协议特定功能，为USB芯片提供了一个简单的重用机制。

公开(公告)号：US08055825B2

公开(公告)日：2011-11-08

申请号：US12762823

申请日：2010-04-19

Applicant: Mark R. Bohm

Inventor： Mark R. Bohm

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F1/3203 ,  G06F1/3253 ,  G06F2213/0042 ,  Y02D10/151

Abstract: A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract translation: 简单的时钟源同步DDR数据传输机制可以与静态总线状态信令组合以用易于实现的数字串行互连总线来代替复杂总线（例如USB）。 这可以消除USB中所需的各种上拉/下拉电阻，并且当总线处于空闲状态或数据传输状态时，使互连总线能够很少或没有泄漏电流工作。 所有必需的功能可以仅使用两个信号引脚来实现。 互连总线还可以为不需要PLL的高速USB启用硅解决方案，因为时钟可以由传输源提供，因此可能不需要从串行数据流中恢复。 数字串行互连总线可以通过使设计人员能够移除模拟PHY并用串行数字I / O传输机制替代它，同时保留IP的USB定时器以及其他协议特定的功能，为USB芯片提供了一个简单的重用机制。

公开(公告)号：US20100205339A1

公开(公告)日：2010-08-12

申请号：US12762823

申请日：2010-04-19

Applicant: Mark R. Bohm

Inventor： Mark R. Bohm

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F1/3203 ,  G06F1/3253 ,  G06F2213/0042 ,  Y02D10/151

Abstract: A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract translation: 简单的时钟源同步DDR数据传输机制可以与静态总线状态信令组合以用易于实现的数字串行互连总线来代替复杂总线（例如USB）。 这可以消除USB中所需的各种上拉/下拉电阻，并且当总线处于空闲状态或数据传输状态时，使互连总线能够很少或没有泄漏电流工作。 所有必需的功能可以仅使用两个信号引脚来实现。 互连总线还可以为不需要PLL的高速USB启用硅解决方案，因为时钟可以由传输源提供，因此可能不需要从串行数据流中恢复。 数字串行互连总线可以通过使设计人员能够移除模拟PHY并用串行数字I / O传输机制替代它，同时保留IP的USB定时器以及其他协议特定的功能，为USB芯片提供了一个简单的重用机制。

公开(公告)号：US07626436B2

公开(公告)日：2009-12-01

申请号：US11939670

申请日：2007-11-14

Applicant: Shawn Shaojie Li ,  Akhlesh Nigam ,  Mark R. Bohm ,  Michael J. Pennell

Inventor： Shawn Shaojie Li ,  Akhlesh Nigam ,  Mark R. Bohm ,  Michael J. Pennell

IPC: G06F1/04

CPC classification number: H03L7/0995

Abstract: An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional pins on the IC, and/or without requiring any additional external information. The ASCDS may be configured with an internal ring oscillator, which may be generated from standard logic elements, a watchdog counter, and an input clock counter. When the IC comes out of power on reset (POR), the ASCDS may compare the input clock counter with the watchdog counter, and determine the clock frequency of the input clock. It may then set the PLL parameters to ensure correct IC operation.

Abstract translation: 自动系统时钟检测系统（ASCDS）可以提供具有检测外部晶体振荡器或时钟源的频率的集成电路（IC），并相应调整IC的内部PLL以进行适当的IC操作。 可以在IC上没有任何额外的引脚进行频率检测和PLL调整，和/或不需要任何额外的外部信息。 ASCDS可以配置有内部环形振荡器，其可以由标准逻辑元件，看门狗计数器和输入时钟计数器产生。 当IC掉电上电（POR）时，ASCDS可以将输入时钟计数器与看门狗计数器进行比较，并确定输入时钟的时钟频率。 然后可以设置PLL参数以确保正确的IC操作。

公开(公告)号：US08352657B2

公开(公告)日：2013-01-08

申请号：US13246365

申请日：2011-09-27

Applicant: Mark R. Bohm

Inventor： Mark R. Bohm

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F1/3203 ,  G06F1/3253 ,  G06F2213/0042 ,  Y02D10/151

Abstract: A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract translation: 简单的数据传输机制可以与静态总线信号组合，以用数字串行互连总线（DSIB）代替USB。 这可以消除USB中所需的各种上拉/下拉电阻，并且当总线处于空闲状态或数据传输状态时，使DSIB能够很少或没有泄漏电流工作。 所有必需的功能可以仅使用两个信号引脚来实现。 DSIB还可以为不需要PLL的高速USB启用硅解决方案，因为时钟可能由传输源提供，因此可能不需要从串行数据流中恢复。 DSIB可以通过使设计人员能够移除模拟PHY并用串行数字I / O传输机制替代它，同时保留IP的USB定时器以及其他协议特定功能，为USB芯片提供了一个简单的重用机制。

公开(公告)号：US07631111B2

公开(公告)日：2009-12-08

申请号：US11465189

申请日：2006-08-17

Applicant: Morgan H. Monks ,  Mark R. Bohm

Inventor： Morgan H. Monks ,  Mark R. Bohm

IPC: G06F3/00 ,  G06F1/00

CPC classification number: H04L12/10 ,  H02J7/0036

Abstract: System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.

Abstract translation: 用于枚举和/或枚举设备的系统和方法。 该设备可以是遵守第一标准（例如USB规范）的USB便携式设备，并且可以参照关于USB集线器/ USB主机设备的枚举。 在设备中包括的电池足够低的情况下，该设备可以从事低功率枚举，例如开始使用枚举功率对设备充电。 低功耗枚举可能允许设备枚举，即使设备无法启动。 另外或替代地，设备可以确定集线器/主设备是否能够提供高功率充电。 如果是，则设备可以使用由集线器/主机设备提供的功率以高功率电平开始对设备的电池充电。

公开(公告)号：US07624202B2

公开(公告)日：2009-11-24

申请号：US11465195

申请日：2006-08-17

Applicant: Morgan H. Monks ,  Mark R. Bohm

Inventor： Morgan H. Monks ,  Mark R. Bohm

IPC: G06F3/00 ,  G06F1/00

CPC classification number: G06F1/266

Abstract: System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.

Abstract translation: 用于枚举和/或枚举设备的系统和方法。 该设备可以是遵守第一标准（例如USB规范）的USB便携式设备，并且可以参照关于USB集线器/ USB主机设备的枚举。 在设备中包括的电池足够低的情况下，该设备可以从事低功率枚举，例如开始使用枚举功率对设备充电。 低功耗枚举可能允许设备枚举，即使设备无法启动。 另外或替代地，设备可以确定集线器/主设备是否能够提供高功率充电。 如果是，则设备可以使用由集线器/主机设备提供的功率以高功率电平开始对设备的电池充电。