公开(公告)号：US11609861B1

公开(公告)日：2023-03-21

申请号：US16947439

申请日：2020-07-31

申请人： Marvell Asia Pte, Ltd.

发明人： Saurabh Shrivastava ,  Shrikant Sundaram ,  Guy T. Hutchison

IPC分类号： G06F12/10 ,  G06F12/06

摘要： A method includes synthetizing a hardware description language (HDL) code into a netlist comprising a first a second and a third components. The method further includes allocating addresses to each component of the netlist. Each allocated address includes assigned addresses and unassigned addresses. An internal address space for a chip is formed based on the allocated addresses. The internal address space includes assigned addresses followed by unassigned addresses for the first component concatenated to the assigned addresses followed by unassigned addresses for the second component concatenated to the assigned addresses followed by unassigned addresses for the third component. An external address space for components outside of the chip is generated that includes only the assigned addresses of the first component concatenated to the assigned addresses of the second component concatenated to the assigned addresses of the third component. Internal addresses are translated to external addresses and vice versa.

公开(公告)号：US11436040B2

公开(公告)日：2022-09-06

申请号：US16947448

申请日：2020-07-31

申请人： Marvell Asia Pte Ltd

发明人： Saurabh Shrivastava ,  Guy T. Hutchison

IPC分类号： G06F9/48 ,  G06F9/54 ,  G06F11/07 ,  G06F9/30 ,  G06F9/38

摘要： A new approach of systems and methods to support a hierarchical interrupt propagation scheme for efficient interrupt propagation and handling is proposed. The hierarchical interrupt propagation scheme organizes a plurality of slave interrupt handlers associated functional blocks in a chip in a hierarchy. When an exception or error condition occurs in a functional block, a slave interrupt handler associated with the functional block creates an interrupt packet as an interrupt notification and utilizes pre-existing input and output interfaces that have already been utilized for accessing registers of the functional block to transmit the created interrupt packet to a central interrupt handler through the hierarchy without running dedicated interconnect wires out of the functional block. The central interrupt handler then processes the interrupt notifications and provides a response packet to the interrupt notification back to slave interrupt handler that created the interrupt packet to configure or adjust the functional block accordingly.