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    Semiconductor memory device having flip-flop circuits
    2.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US5132771A

    公开(公告)日：1992-07-21

    申请号：US503928

    申请日：1990-04-04

    申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    IPC分类号： G11C11/412 ,  H01L27/11

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

    摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

    摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。

    Process for making MOS devices for low-temperature operation
    3.
    发明授权
    Process for making MOS devices for low-temperature operation 失效
    制造用于低温操作的MOS器件的方法

    公开(公告)号：US5091325A

    公开(公告)日：1992-02-25

    申请号：US544045

    申请日：1990-06-26

    申请人： Shoji Hanamura ,  Masaaki Aoki ,  Toshiaki Masuhara

    发明人： Shoji Hanamura ,  Masaaki Aoki ,  Toshiaki Masuhara

    IPC分类号： G11C8/18 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H03K5/1534 ,  H03K19/00

    CPC分类号： H03K5/1534 ,  G11C8/18 ,  H01L27/092 ,  H01L27/10805 ,  H03K19/0016 ,  H01L27/105

    摘要： Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized. Also disclosed is a semiconductor device, and method of forming such semiconductor device, for operation in a range of temperatures below 100.degree. K. The device has, in a silicon surface region where the channel of the device is formed, a low impurity concentration layer (between the source and drain regions of the device). Such low impurity concentration layer is formed by evaporating amorphous silicon on a surface region of a semiconductor region of the device and passing the device through a low-temperature annealing process, the low impurity concentration layer having a lower total impurity concentration than that of the semiconductor region thereunder and having a thickness not more than 100 nm.

    Semiconductor memory device and sense amplifier
    6.
    发明授权
    Semiconductor memory device and sense amplifier 失效
    半导体存储器件和读出放大器

    公开(公告)号：US4841486A

    公开(公告)日：1989-06-20

    申请号：US946776

    申请日：1986-12-29

    申请人： Osamu Minato ,  Toshiaki Masuhara ,  Koichiro Ishibashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki

    发明人： Osamu Minato ,  Toshiaki Masuhara ,  Koichiro Ishibashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki

    IPC分类号： H01L27/11 ,  G11C7/06 ,  G11C11/416 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/10

    CPC分类号： G11C11/419 ,  G11C7/062

    摘要： A semiconductor memory device having a memory plane defined by a plurality of memory cells, a decoder line for accessing the memory cells, a common data line on which a signal output from an accessed memory cell is collected, and a sense amplifier for amplifying the signal collected on the common data line. The sense amplifier has an amplifying circuit portion which is composed of a pair of common-collector type bipolar transistors supplied with the signal collected on the common data line as a differential input, and a plurality of MOS transistors for converting a change in current into a change in voltage. Each of the MOS transistors has a lightly-doped drain structure.

    摘要翻译： 一种具有由多个存储单元限定的存储器平面的半导体存储器件，用于访问存储器单元的解码器线，从所访问的存储单元输出的信号被收集的公共数据线，以及用于放大该信号的读出放大器 在公共数据线上收集。 读出放大器具有放大电路部分，该放大电路部分由一对公共集电极型双极晶体管构成，该一对公共集电极型双极晶体管被提供有作为差分输入的公共数据线上收集的信号，以及多个MOS晶体管，用于将电流变化转换为 电压变化。 每个MOS晶体管具有轻掺杂漏极结构。

    Semiconductor memory with automatic refresh means
    7.
    发明授权
    Semiconductor memory with automatic refresh means 失效
    具有自动刷新功能的半导体存储器

    公开(公告)号：US4747082A

    公开(公告)日：1988-05-24

    申请号：US76174

    申请日：1987-07-21

    申请人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

    发明人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

    IPC分类号： G11C11/406 ,  G11C8/00

    CPC分类号： G11C11/406

    摘要： A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.

    摘要翻译： 半导体存储器设置有自动刷新装置，包括定时器，刷新计数器和刷新缓冲器，每个形成在安装有异步存储器的半导体芯片上，用于基于生成的基本时钟信号自动执行周期性刷新操作 响应于对刷新计数器的输出的逻辑改变的检测。 自动刷新计数器包括优先于周期性刷新操作执行基于与周期性刷新操作异步的常规地址信号的读操作和写操作之一的装置。

    Static type semiconductor memory
    9.
    发明授权
    Static type semiconductor memory 失效
    静态型半导体存储器

    公开(公告)号：US5088065A

    公开(公告)日：1992-02-11

    申请号：US593584

    申请日：1990-10-05

    申请人： Shoji Hanamura ,  Masaaki Kubotera ,  Katsuro Sasaki ,  Takao Oono ,  Kiyotsugu Ueda

    发明人： Shoji Hanamura ,  Masaaki Kubotera ,  Katsuro Sasaki ,  Takao Oono ,  Kiyotsugu Ueda

    IPC分类号： G11C7/06 ,  G11C11/419

    CPC分类号： G11C7/062 ,  G11C11/419

    摘要： Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage sense amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.

    摘要翻译： 从静态半导体存储器的存储单元读出的信息在初级读出放大器，后级读出放大器和主放大器中进行多级感测放大，然后传输到输出缓冲电路的输入端。 由于均衡电路连接到多级读出放大器的各级的互补输入，所以可以高速执行反向信息读取操作。 最初，初级读出放大器，后级读出放大器和主放大器被控制为在高放大增益条件下工作，以便执行高速感测放大，此后被控制以在低功耗条件下工作， 通过高速感测放大获得的输出信息输出不会消失。

    Sense amplifier for a memory device
    10.
    发明授权
    Sense amplifier for a memory device 失效
    用于存储器件的感应放大器

    公开(公告)号：US5126974A

    公开(公告)日：1992-06-30

    申请号：US465040

    申请日：1990-01-16

    申请人： Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Koichiro Ishibashi ,  Shoji Hanamura

    发明人： Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Koichiro Ishibashi ,  Shoji Hanamura

    IPC分类号： G11C7/06 ,  G11C11/419

    CPC分类号： G11C7/062 ,  G11C11/419 ,  G11C7/065

    摘要： A MOS transistor sense amplifier employs cross coupled positive feedback for the load circuit of a differential amplifier with an equalizing switch at the amplifier output, and preferably also at the input. This basis amplifier circuit may be repeated in stages. When stages are employed, it is desirable that the first stage employs current mirror loading of the differential amplifier to reduce the data delay. Data delay is further reduced by providing strong amplification during the sense portion of the read cycle with a preamplifier, which preamplifier has its amplification reduced, preferably to unity by being turned off, when the sense portion of the cycle is finished, and most preferably when the input and output data lines are directly connected independently of the preamplifier, so that the preamplifier may be completely turned off to lower power consumption.

    摘要翻译： MOS晶体管感测放大器采用交叉耦合的正反馈给差分放大器的负载电路，在放大器输出端具有均衡开关，优选也在输入端。 该基本放大器电路可以分阶段地重复。 当采用级时，期望第一级采用差分放大器的电流镜像负载来减少数据延迟。 通过在读周期的感测部分期间通过在前置放大器上提供强放大来进一步降低数据延迟，当循环的感测部分完成时，前置放大器的放大减小，优选地被关闭，优选地，当 输入和输出数据线独立于前置放大器直接连接，从而可以完全关闭前置放大器以降低功耗。