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1.发明授权System for controlling data flow between plurality of host interfaces and drive interfaces using controller for select unoccupied interfaces after preparation of read/write operation is complete 失效用于在准备读/写操作之后使用控制器控制多个主机接口和驱动器接口之间用于选择未占用接口的数据流的系统完成
公开(公告)号：US5603062A
公开(公告)日：1997-02-11
申请号：US148484
申请日：1993-11-08
申请人： Masahiko Sato , Kazuo Nakagoshi , Naoya Takahashi , Akira Chuma , Yoshio Yukawa
发明人： Masahiko Sato , Kazuo Nakagoshi , Naoya Takahashi , Akira Chuma , Yoshio Yukawa
CPC分类号： G06F3/0601 , G06F2003/0691 , G06F2003/0692
摘要： An external storage system is connected to a host system. A controller unit interposed between disk drives and the host system has a large capacity buffer memory with a battery providing non-volatile storage, a plurality of host interfaces and a plurality of drive interfaces. All the accesses made to the disk drives from the host system are realized via the buffer memory which allows a high-speed access. Read/write processing performed for the buffer memory by the host system is executed asynchronously with read/write processing performed between the buffer memory and the disk drives. The drive interface and the host interface area released during a period in which operation of the disk drive is waited for and recoupled upon data transfer.
摘要翻译： 外部存储系统连接到主机系统。 插入在盘驱动器和主机系统之间的控制器单元具有大容量缓冲存储器，其中电池提供非易失性存储器，多个主机接口和多个驱动接口。 通过缓冲存储器实现从主机系统到磁盘驱动器的所有访问，这允许高速访问。 由主机系统对缓冲存储器执行的读/写处理与缓冲存储器和磁盘驱动器之间执行的读/写处理异步执行。 驱动器接口和主机接口区域在数据传输期间等待并重新连接磁盘驱动器的操作期间释放。
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公开(公告)号：US5606706A
公开(公告)日：1997-02-25
申请号：US293624
申请日：1994-08-22
CPC分类号： G06F11/1435 , G06F12/0866 , G06F2212/401 , Y10S707/99953 , Y10S707/99955
摘要： The write data is entered from the upper unit into a nonvolatile cache provided in a controller inside of each disk unit through a channel adaptor, a cache shared by each disk, and a disk adaptor. The data from the cache is compressed by the data compressing and restoring device and is written in the disk. At a time, the management information for compressed data is written in the cache and the disk as well. In case of breaking the management information of the cache when a failure takes place in the cache memory, the management information is written for each disk. Hence, the breakage does not have an adverse effect on the other disks. If the management information of the cache is broken, the management information given into the disk may be replaced with the broken information.
摘要翻译： 写入数据通过通道适配器，由每个磁盘共享的高速缓存器和磁盘适配器从上位机输入到每个磁盘单元内的控制器中提供的非易失性缓存。 来自缓存的数据由数据压缩和恢复设备压缩并写入磁盘。 一次，压缩数据的管理信息也被写入高速缓存和磁盘。 在高速缓冲存储器中发生故障时破坏缓存的管理信息的情况下，为每个盘写入管理信息。 因此，破损对其他磁盘没有不利影响。 如果高速缓存的管理信息被破坏，则可以用损坏的信息替换给予该盘的管理信息。
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公开(公告)号：US5546348A
公开(公告)日：1996-08-13
申请号：US359787
申请日：1994-12-20
IPC分类号： G11C17/00 , G06F3/06 , G06F11/00 , G06F12/08 , G11C16/02 , G11C16/34 , G11C29/00 , G11C13/00
CPC分类号： G11C29/76 , G06F12/08 , G06F3/0601 , G11C16/349 , G11C16/3495 , G06F11/076 , G06F2003/0694 , G06F2201/88
摘要： A semiconductor storage device is connected to at least one magnetic storage device. The input and output of data is made between the semiconductor storage device and an information processing device. The semiconductor storage device includes an electrically erasable non-volatile semiconductor memory which stores directory information of data stored in the magnetic storage device, a volatile semiconductor memory which has a storage capacity smaller than that of the non-volatile semiconductor memory and the storage contents of which are updated to store a part of the directory information having a higher frequency of access from the information processing device, and a CPU connected to the volatile semiconductor memory and the non-volatile semiconductor memory for making access to the volatile semiconductor memory and the non-volatile semiconductor memory in accordance with an access request from the information processing device, wherein when access to the volatile semiconductor memory made for access from the information processing device to the magnetic storage device hits on the part of the directory information, the CPU transfers the part of the directory information to the information processing device without making access to the non-volatile semiconductor memory and the information processing device makes access to the magnetic storage device on the basis of the part of the directory information When a failure is generated in the non-volatile semiconductor memory or when a predicted service life of the non-volatile semiconductor memory is elapsed, the non-volatile semiconductor memory is substituted by an alternate memory.
摘要翻译： 半导体存储装置连接到至少一个磁存储装置。 在半导体存储装置和信息处理装置之间进行数据的输入和输出。 半导体存储装置包括：电可擦除非易失性半导体存储器，其存储存储在磁存储装置中的数据的目录信息;易失性半导体存储器，其存储容量小于非易失性半导体存储器的存储容量;存储容量 其被更新以存储来自信息处理装置的具有较高访问频率的目录信息的一部分，以及连接到易失性半导体存储器和非易失性半导体存储器以用于访问易失性半导体存储器和非易失性半导体存储器的CPU的CPU， 根据来自所述信息处理装置的访问请求，所述非易失性半导体存储器，其中，当访问由所述信息处理装置访问的所述易失性半导体存储器到所述磁存储装置时，所述CPU转移所述目录信息的一部分， 信息的一部分目录信息 在不进入非易失性半导体存储器的情况下，信息处理装置和信息处理装置根据目录信息的一部分访问磁存储装置当在非易失性半导体存储器中产生故障时，或者当 经过非易失性半导体存储器的预期使用寿命，非替换存储器代替非易失性半导体存储器。
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公开(公告)号：US5606529A
公开(公告)日：1997-02-25
申请号：US612618
申请日：1996-03-06
CPC分类号： G06F3/0601 , G06F12/0866 , G06F2003/0694 , G06F2212/2022 , G06F2212/312
摘要： A semiconductor storage device transfers data with an information processing device and includes a non-volatile semiconductor memory in which data is electrically re-writable, a volatile semiconductor memory connected to the non-volatile memory and temporarily storing data of the non-volatile semiconductor memory, and a CPU connected to the volatile semiconductor memory and the non-volatile semiconductor memory. The CPU controls the transfer of data among the non-volatile memory, the volatile memory and the CPU. The CPU also transfers data with the information processing device in accordance with a fixed-length form for data. When an access from the CPU to the volatile semiconductor makes a miss hit (i.e., misses), the CPU accesses the non-volatile semiconductor memory. When a failure is generated in the non-volatile semiconductor memory or when a predicted service life of the non-volatile semiconductor memory is elapsed, the non-volatile semiconductor memory can be substituted by an alternate memory.
摘要翻译： 半导体存储装置与信息处理装置传送数据，并且包括数据可重写的非易失性半导体存储器，与非易失性存储器连接的易失性半导体存储器，并临时存储非易失性半导体存储器的数据 连接到易失性半导体存储器和非易失性半导体存储器的CPU。 CPU控制非易失性存储器，易失性存储器和CPU之间的数据传输。 CPU还根据数据的固定长度形式与信息处理设备传输数据。 当从CPU到易失性半导体的访问造成未命中（即错过）时，CPU访问非易失性半导体存储器。 当在非易失性半导体存储器中产生故障时，或者当经过非易失性半导体存储器的预计使用寿命时，非易失性半导体存储器可以被备用存储器代替。
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5.发明授权Data storing system and data transfer method with a plurality of disk units 失效具有多个盘单元的数据存储系统和数据传送方法
公开(公告)号：US5392445A
公开(公告)日：1995-02-21
申请号：US89144
申请日：1993-07-07
CPC分类号： G06F11/1435 , G06F12/0866 , G06F2212/401 , Y10S707/99953 , Y10S707/99955
摘要： The write data is entered from the upper unit into a nonvolatile cache provided in a controller inside of each disk unit through a channel adaptor, a cache shared by each disk, and a disk adaptor. The data from the cache is compressed by the data compressing and restoring device and is written in the disk. At a time, the management information for compressed data is written in the cache and the disk as well. In case of breaking the management information of the cache when a failure takes place in the cache memory, the management information is written for each disk. Hence, the breakage does not have an adverse effect on the other disks. If the management information of the cache is broken, the management information given into the disk may be replaced with the broken information.
摘要翻译： 写入数据通过通道适配器，每个磁盘共享的高速缓存和磁盘适配器从上位机输入到每个磁盘单元内的控制器中提供的非易失性缓存。 来自缓存的数据由数据压缩和恢复设备压缩并写入磁盘。 一次，压缩数据的管理信息也被写入高速缓存和磁盘。 在高速缓冲存储器中发生故障时破坏缓存的管理信息的情况下，为每个盘写入管理信息。 因此，破损对其他磁盘没有不利影响。 如果高速缓存的管理信息被破坏，则可以用损坏的信息替换给予该盘的管理信息。
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公开(公告)号：US20060248245A1
公开(公告)日：2006-11-02
申请号：US11476699
申请日：2006-06-29
申请人： Tatuya Ninomiya , Hidefumi Masuzaki , Hiroyuki Kurosawa , Naoya Takahashi , Yasuo Inoue , Hidehiko Iwasaki , Masayuki Hoshino , Soichi Isono
发明人： Tatuya Ninomiya , Hidefumi Masuzaki , Hiroyuki Kurosawa , Naoya Takahashi , Yasuo Inoue , Hidehiko Iwasaki , Masayuki Hoshino , Soichi Isono
IPC分类号： G06F13/12
CPC分类号： G06F3/0601 , G06F3/0607 , G06F3/0658 , G06F3/0689 , G06F11/1076 , G06F11/1641 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F11/201 , G06F11/2089 , G06F12/0866 , G06F2003/0692 , G06F2201/85 , G06F2211/1009 , G06F2212/261 , G06F2212/312 , G11C29/88
摘要： A storage system to be connected to a large-scale computer includes a plurality of host adaptors connected to a host device, a plurality of storage device for storing data from the host device, a plurality of disk adaptors connected to the storage devices, a plurality of caches for temporarily storing data transferred between the host adaptors and the disk adaptors, and two buses connected to the host disk adaptors, and the caches. The buses transfer data among the host and disk adaptors and the caches.
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公开(公告)号：US06463505B2
公开(公告)日：2002-10-08
申请号：US09883179
申请日：2001-06-19
申请人： Eiju Katsuragi , Mikito Ogata , Akira Kurano , Toshihiko Tamiya , Akira Yamamoto , Naoya Takahashi
发明人： Eiju Katsuragi , Mikito Ogata , Akira Kurano , Toshihiko Tamiya , Akira Yamamoto , Naoya Takahashi
IPC分类号： G06F1216
CPC分类号： G06F11/1076 , G06F2211/1054 , G06F2211/1066
摘要： A disk array device selects a redundant generation method for reducing the overhead and improving the reliability associated with generating redundant data. The disk array device includes a disk controller connected to and controlling an array of disk drives. The disk controller includes a redundant data generator, a difference data generator, and a redundant data generation method selector. The redundant data generator is able to generate redundant data via a read and modify method and an all stripes method. The disk array device selects a method of generating redundant data from a method of read and modify and all stripes, and a method of generation in a drive and a method of difference, both of which are executed to generate redundant data on a disk drive. The disk array device selects the method of generating redundant data that will minimize the time required to process, transfer and store both the received host data and the generated redundant data based on the length of write data received from the host, an access pattern specified by the host, by the current load state of the disk drives, and by the existence of a failure state in a disk drive. Divided write data and previous data to be updated may be transferred depending on the write data length.
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公开(公告)号：US06321185B1
公开(公告)日：2001-11-20
申请号：US09252891
申请日：1999-02-19
申请人： Naoya Takahashi
发明人： Naoya Takahashi
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F2217/78
摘要： Power consumption of an LSI chip is estimated at the beginning stage of the designing without using the HDL description. An I/O part power of a new designing LSI chip is calculated by an equation with using the outside specifications required by the application of the LSI chip. An I/O part power of an original LSI chip is calculated by the outside specifications, the core circuitry part power of the original LSI chip is calculated by subtracting this calculated I/O part power of the original LSI chip from the known total power of the original LSI chip, and converting the voltage and process and frequency, the core circuitry part power of the new designing LSI chip is calculated. The kinds of functions, voltage, frequency, the number of gates, unit capacity and clock structure of the new designing LSI chip are given and referring to the data base of ratio of each function described the ratio of the number of FF and the ratio of clock power/logic power, the clock system power is calculated by the number of FF and the clock structure. The logic system power is calculated by the ratio of the clock power/the logic power. The modifiable circuitry part power is calculated by summing up the I/O part power, the core circuitry part power, the clock system power and the logic system power.
摘要翻译： 在设计的初始阶段估计LSI芯片的功耗，而不使用HDL描述。 通过使用LSI芯片的应用所要求的外部规格的方程式来计算新的设计LSI芯片的I / O部分功率。 通过外部规格计算原始LSI芯片的I / O部分功率，通过从原始LSI芯片的已知总功率中减去该计算出的原始LSI芯片的I / O部分功率来计算原始LSI芯片的核心电路部分功率 原来的LSI芯片，并且转换电压和处理和频率，计算出新的设计LSI芯片的核心电路部分功率。 给出了新的设计LSI芯片的功能，电压，频率，门数，单元容量和时钟结构的种类，并参考了每个功能的比率的数据库，描述了FF的数量和比率 时钟功率/逻辑电源，时钟系统功率由FF和时钟结构的数量计算。 逻辑系统功率由时钟功率/逻辑功率的比率计算。 通过对I / O部分功率，核心电路部分功率，时钟系统功率和逻辑系统功率相加来计算可修改的电路部分功率。
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公开(公告)号：US6116096A
公开(公告)日：2000-09-12
申请号：US142991
申请日：1998-09-18
申请人： Naoya Takahashi , Masaya Tsuchie
发明人： Naoya Takahashi , Masaya Tsuchie
CPC分类号： G01G19/12
摘要： A structure for attaching a sensing element for measuring load on a vehicle to a slide plate can reduce the number of components and gives good detection sensitivity. Mounting holes are made at an angle of about 20.degree. at both ends of an internal curved surface of the slide plate. Sensing elements each is secured in each the mounting holes. A wiring plate is placed centrally on a concave portion of the internal curved surface of said slide plate and is used to integrate lead wires from the sensing elements and extend them externally. The wiring plate and lead wires are molded.
摘要翻译： PCT No.PCT / JP96 / 01030 Sec。 371日期：1998年9月18日 102（e）1998年9月18日PCT PCT 1996年4月15日PCT公布。 第WO97 / 39316号公报 日期1997年10月23日用于将用于测量车辆上的负载的感测元件附接到滑板的结构可以减少部件数量并且提供良好的检测灵敏度。 在滑板的内部弯曲表面的两端安装有大约20°的角度。 感测元件各自固定在每个安装孔中。 布线板放置在所述滑板的内部曲面的凹部的中央，用于将来自传感元件的引线与外部的引线相连。 布线板和导线被模制。
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10.发明授权Storage system having a semiconductor memory device which stores data and parity data permanently 失效存储系统具有永久地存储数据和奇偶校验数据的半导体存储器件公开(公告)号：US07444467B2
公开(公告)日：2008-10-28
申请号：US11476699
申请日：2006-06-29
申请人： Tatuya Ninomiya , Hidefumi Masuzaki , Hiroyuki Kurosawa , Naoya Takahashi , Yasuo Inoue , Hidehiko Iwasaki , Masayuki Hoshino , Soichi Isono
发明人： Tatuya Ninomiya , Hidefumi Masuzaki , Hiroyuki Kurosawa , Naoya Takahashi , Yasuo Inoue , Hidehiko Iwasaki , Masayuki Hoshino , Soichi Isono
IPC分类号： G06F12/02
CPC分类号： G06F3/0601 , G06F3/0607 , G06F3/0658 , G06F3/0689 , G06F11/1076 , G06F11/1641 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F11/201 , G06F11/2089 , G06F12/0866 , G06F2003/0692 , G06F2201/85 , G06F2211/1009 , G06F2212/261 , G06F2212/312 , G11C29/88
摘要： A storage system, coupled to a host computer, including at least one controller receiving data from the host computer, and a plurality of memory units connected to the controller. The controller generates parity data and sends the data and the parity data to the memory units. The memory units include a semiconductor memory device which stores the data and the parity data permanently.
摘要翻译： 耦合到主计算机的存储系统，包括从主计算机接收数据的至少一个控制器，以及连接到控制器的多个存储器单元。 控制器产生奇偶校验数据，并将数据和奇偶校验数据发送到存储单元。 存储单元包括一个永久存储数据和奇偶校验数据的半导体存储器件。
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