公开(公告)号：US07083244B2

公开(公告)日：2006-08-01

申请号：US10649545

申请日：2003-08-26

申请人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

发明人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

IPC分类号： B41J29/38 ,  B41J2/205 ,  G03F3/08

CPC分类号： G06K15/102 ,  G06F13/28

摘要： If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.

摘要翻译： 如果与记录数据无关的数据被存储在存储在接收缓冲器单元中的游程长度压缩记录数据的头字数据的较低地址中，则包含头字节的字数据的低位地址的不相关字节数据 数据由解码电路开发的掩码无效。 否则，关于作为DMA传送目的地的本地存储器的位图区域，传输地址由开发处理控制器以存储在行缓冲器中的开发的记录数据的每个单词的DECU单独设置，以便数据 将一行排列并存储在垂直方向上，或者一行的数据依次存储在图像1和图像2中。 否则，关于开发处理控制器，当由解码电路开发的记录数据存储在行缓冲器中时，在行缓冲器的第0字节空闲的状态下从第一字节存储。

公开(公告)号：US20060187248A1

公开(公告)日：2006-08-24

申请号：US11408280

申请日：2006-04-19

申请人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

发明人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

IPC分类号： B41J29/38

CPC分类号： G06K15/102 ,  G06F13/28

摘要： If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.

公开(公告)号：US07167932B2

公开(公告)日：2007-01-23

申请号：US10649296

申请日：2003-08-26

申请人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

发明人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

IPC分类号： G06F13/00 ,  H04N7/12

CPC分类号： G06K15/102 ,  G06K15/00

摘要： Compressed recording data is DMA-transferred to a receiving buffer unit via a system bus one word each. It is DMA-transferred from the receiving buffer unit to a DECU via the system bus. It is developed based on hardware by a decode circuit in the DECU, and stored in a line buffer. It is DMA-transferred to a local memory via a local bus when it reaches predetermined bytes. The recording data stored in the local memory is DMA-transferred to the DECU via the local bus, DMA-transferred to a head controlling unit and DMA-transferred to a recording head.

摘要翻译： 压缩记录数据通过系统总线DMA传输到接收缓冲单元，每个字母一个字。 它通过系统总线从接收缓冲单元DMA传输到DECU。 它是通过DECU中的解码电路基于硬件开发的，并存储在行缓冲区中。 当达到预定字节时，DMA通过本地总线传输到本地存储器。 存储在本地存储器中的记录数据通过本地总线DMA传送到DECU，DMA传送到头控制单元，DMA传送到记录头。

公开(公告)号：US07458652B2

公开(公告)日：2008-12-02

申请号：US11408280

申请日：2006-04-19

申请人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

发明人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

IPC分类号： B41J29/38

CPC分类号： G06K15/102 ,  G06F13/28

摘要： If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.

摘要翻译： 如果与记录数据无关的数据被存储在存储在接收缓冲器单元中的游程长度压缩记录数据的头字数据的较低地址中，则包含头字节的字数据的低位地址的不相关字节数据 数据由解码电路开发的掩码无效。 否则，关于作为DMA传送目的地的本地存储器的位图区域，传输地址由开发处理控制器以存储在行缓冲器中的开发的记录数据的每个单词的DECU单独设置，以便数据 将一行排列并存储在垂直方向上，或者一行的数据依次存储在图像1和图像2中。 否则，关于开发处理控制器，当由解码电路开发的记录数据存储在行缓冲器中时，在行缓冲器的第0字节空闲的状态下从第一字节存储。

公开(公告)号：US20090179688A1

公开(公告)日：2009-07-16

申请号：US12318934

申请日：2009-01-13

申请人： Masahiro Igarashi ,  Tetsuo Motomura ,  Ryuji Kaneko ,  Makoto Fujiwara ,  Yoshinori Tanaka ,  Hiromi Ogata

发明人： Masahiro Igarashi ,  Tetsuo Motomura ,  Ryuji Kaneko ,  Makoto Fujiwara ,  Yoshinori Tanaka ,  Hiromi Ogata

IPC分类号： H03K17/687

CPC分类号： H03K17/164 ,  H03K17/102 ,  H03K19/0016

摘要： A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.

摘要翻译： 半导体集成电路包括：第一电压线，其中出现电源电压和参考电压中的特定一个; 第二电压线; 多个电路单元，每个电路单元接收作为所述第二电压线上出现的电压和所述电源电压和所述参考电压中的另一个之间的差产生的功率; 多个开关晶体管并联连接在第一和第二电压线之间，用作包括具有不同导通状态电阻的开关晶体管的开关晶体管; 以及开关导通控制部分，用于通过在分开的时间点导通开关晶体管来控制每个开关晶体管从非导通状态到导通状态的转变。

公开(公告)号：US07956677B2

公开(公告)日：2011-06-07

申请号：US12318934

申请日：2009-01-13

申请人： Masahiro Igarashi ,  Tetsuo Motomura ,  Ryuji Kaneko ,  Makoto Fujiwara ,  Yoshinori Tanaka ,  Hiromi Ogata

发明人： Masahiro Igarashi ,  Tetsuo Motomura ,  Ryuji Kaneko ,  Makoto Fujiwara ,  Yoshinori Tanaka ,  Hiromi Ogata

IPC分类号： H03K17/72

CPC分类号： H03K17/164 ,  H03K17/102 ,  H03K19/0016

摘要： A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.

摘要翻译： 半导体集成电路包括：第一电压线，其中出现电源电压和参考电压中的特定一个; 第二电压线; 多个电路单元，每个电路单元接收作为所述第二电压线上出现的电压和所述电源电压和所述参考电压中的另一个之间的差产生的功率; 多个开关晶体管并联连接在第一和第二电压线之间，用作包括具有不同导通状态电阻的开关晶体管的开关晶体管; 以及开关导通控制部分，用于通过在分开的时间点导通开关晶体管来控制每个开关晶体管从非导通状态到导通状态的转变。

公开(公告)号：US07151862B2

公开(公告)日：2006-12-19

申请号：US10299297

申请日：2002-11-19

申请人： Tanio Nagasaki ,  Hideaki Tomikawa ,  Seigo Iwasaki ,  Tetsuo Motomura ,  Masahiro Igarashi

发明人： Tanio Nagasaki ,  Hideaki Tomikawa ,  Seigo Iwasaki ,  Tetsuo Motomura ,  Masahiro Igarashi

IPC分类号： G06K9/32 ,  G06K9/36

CPC分类号： G06T15/04 ,  G06T2210/36

摘要： Texture data filtered according to each of different reduction ratio are stored in a texture buffer. A texture mapping apparatus (an lod calculating apparatus) calculates an lod (Level Of Detail) which represents a reduction ratio of each pixel of a polygon. The calculation does not include a divisional calculation. In other words, the lod calculating apparatus does not need many multipliers, as compared with a case in which an operation including a divisional calculation, thereby enabling the down-sizing of the lod calculating apparatus.

公开(公告)号：US06940512B2

公开(公告)日：2005-09-06

申请号：US10441546

申请日：2003-05-20

申请人： Yuji Yamaguchi ,  Jin Satoh ,  Masahiro Igarashi

发明人： Yuji Yamaguchi ,  Jin Satoh ,  Masahiro Igarashi

IPC分类号： G06F15/16 ,  G06F15/80 ,  G06F17/10 ,  G06T1/20 ,  G06T15/00

CPC分类号： G06T1/20

摘要： An image processing apparatus able to efficiently utilize a large amount of operation processing elements, having a high degree of freedom of algorithms, and having a high flexibility, provided with a rasterizer for generating pixel data or addresses; a graphics unit for generating graphics data based on texture coordinates; a pixel operation processor for performing operations based on the graphics data and performing image processing with respect to the image data in accordance with source addresses at the time of image processing; a pixel engine for performing operations with respect to the operation data of the pixel operation processor set in a register based on the color data; and a write unit for performing processing required for pixel writing based on window coordinates and the operation data of the pixel engine set in the register at the time of graphics processing and writing the processing results into a memory according to need and writing the operation data of the pixel operation processor set in the register at a destination address of the memory at the time of image processing, and a method of the same.

摘要翻译： 一种图像处理装置，其能够高效地利用具有高自由度的算法的高度的自由度的操作处理元件，并且具有高的灵活性，具有用于生成像素数据或地址的光栅化器; 用于基于纹理坐标生成图形数据的图形单元; 像素运算处理器，用于根据图形数据执行操作，并根据图像处理时的源地址对图像数据执行图像处理; 一个像素引擎，用于根据颜色数据对寄存器中设置的像素运算处理器的运算数据执行操作; 以及写入单元，用于根据窗口坐标执行像素写入所需的处理以及在图形处理时在寄存器中设置的像素引擎的操作数据，并根据需要将处理结果写入存储器并写入操作数据 在图像处理时在存储器的目的地地址处设置在寄存器中的像素运算处理器及其方法。

公开(公告)号：US5305653A

公开(公告)日：1994-04-26

申请号：US951154

申请日：1992-09-25

申请人： Yukio Ohtani ,  Satoshi Uehara ,  Masahiro Igarashi ,  Hiroshi Suzuki

发明人： Yukio Ohtani ,  Satoshi Uehara ,  Masahiro Igarashi ,  Hiroshi Suzuki

IPC分类号： B25J17/02 ,  B25J18/00

CPC分类号： B25J17/0283 ,  Y10T74/20317

摘要： A robot wrist mechanism such as those used for painting, sealing and welding operations is disclosed. The robot wrist mechanism comprises an arm rotated by a drive source; a first wrist member rotatably supported on the end of the arm so as to be rotatable about a first rotation axis; a second wrist member supported at another end of the first wrist member so as to be freely rotatable about a second rotation axis. The second axis and the arm axis are arranged to lie in the same plane. A mounting shaft is provided on the second wrist member with an axis of the mounting shaft lying in a plane including the first axis and orthogonal to the second axis. The second wrist member is arranged to protrude upwards with respect to a plane including the first axis and the axis of the mounting shaft. With the robot wrist mechanism of the present invention, the drive mechanism transmitting the drive force of the drive shaft to the mounting shaft protrudes upwards of a line through the mounting shaft and arm. As a result, the operability of a robot having this arm during direct teaching is greatly improved.

摘要翻译： 公开了一种诸如用于喷涂，密封和焊接操作的机器人手腕机构。 机器人手腕机构包括由驱动源旋转的臂; 第一腕部构件，其被可旋转地支撑在所述臂的端部上，以便能够围绕第一旋转轴线旋转; 第二腕部构件，其被支撑在所述第一腕构件的另一端，以能够绕第二旋转轴线自由转动。 第二轴和臂轴布置在同一平面内。 安装轴设置在第二腕构件上，安装轴的轴线位于包括第一轴线并与第二轴线正交的平面中。 第二腕构件被布置成相对于包括第一轴线和安装轴的轴线的平面向上突出。 利用本发明的机器人手腕机构，将驱动轴的驱动力传递到安装轴的驱动机构通过安装轴和臂向上突出。 结果，在直接教学中具有该臂的机器人的可操作性大大提高。