公开(公告)号：US4833342A

公开(公告)日：1989-05-23

申请号：US192667

申请日：1988-05-10

申请人： Masakazu Kiryu ,  Hiroyuki Koinuma ,  Kiminobu Suzuki

发明人： Masakazu Kiryu ,  Hiroyuki Koinuma ,  Kiminobu Suzuki

IPC分类号： H01L27/04 ,  G05F3/24 ,  H01L21/822 ,  H01L27/06

CPC分类号： G05F3/247

摘要： A reference potential generating circuit according to this invention includes a first insulated gate field effect transistor of an enhancement type, a second insulated gate field effect transistor of a depletion type and a voltage dividing circuit. The source of the first insulated gate field effect transistor is connected to the ground terminal, and the drain and gate thereof are connected to one another. The drain of the second insulated gate field effect transistor is connected to the power source and the gate thereof is connected to a connection node which connects the drain and gate of the first insulated gate field effect transistor. The voltage dividing circuit is connected between the drain of the first insulated gate field effect transistor and the source of the second insulated gate field effect transistor.

公开(公告)号：US4678934A

公开(公告)日：1987-07-07

申请号：US884629

申请日：1986-07-11

申请人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

发明人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

IPC分类号： G11C11/40 ,  G11C8/06 ,  H03K3/356 ,  H03K3/26 ,  G11C7/00 ,  H03K17/687 ,  H03K19/094

CPC分类号： H03K3/356026 ,  G11C8/06

摘要： A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor, having a current path connected between the gate of the first MOS transistor and the first output terminal and a gate connected to the first output terminal, for charging the gate of the first MOS transistor when the gate potential of the first MOS transistor is dropped a predetermined level in comparison with that of the first output terminal.

摘要翻译： 触发器电路具有设置在5V的电源端子，第一和第二输出端子，用于将第一和第二端子中的一个充电至5V并将第一和第二端子中的另一个放电至0V的锁存部分 根据输入信号，具有连接在电源和第一输出端子之间的电流路径的第一MOS晶体管，第二MOS晶体管，用于对第一MOS晶体管的栅极充电，同时第二输出端子的电位从5V变为 0V，以及用于自举第一MOS晶体管的栅极电位以使第一MOS晶体管导通的电容器。 触发器电路还包括第三MOS晶体管，其具有连接在第一MOS晶体管的栅极和第一输出端子之间的电流路径和连接到第一输出端子的栅极，用于对第一MOS晶体管的栅极充电， 与第一输出端子相比，第一MOS晶体管的栅极电位下降到预定水平。

公开(公告)号：US20070283303A1

公开(公告)日：2007-12-06

申请号：US11742287

申请日：2007-04-30

申请人： Shigeo OHSHIMA ,  Kiminobu Suzuki

发明人： Shigeo OHSHIMA ,  Kiminobu Suzuki

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The verification equipment of a semiconductor integrated circuit in the present invention is included with a circuit net list extraction section that extracts the net list of a circuit, a circuit simulation execution section that executes a circuit simulation, based on the extracted net list, a finite impedance judgment section that judges existence or nonexistence of finite impedances, a floating error terminal judgment section that judges existence or nonexistence of floating error terminals by measuring finite impedances, a true floating error terminal judgment section that adds any one of a P channel-type transistor and an N channel-type transistor to terminals of the circuit where it is judged that there are floating error terminals and calculates changes in potential at the terminals and adds the other of the P channel-type transistor and the N channel-type transistor to the terminals and calculates changes in potential at the terminals, and an output section that outputs a judgment result of the floating error terminal judgment section and a judgment result of the true floating error terminal judgment section.

摘要翻译： 本发明的半导体集成电路的验证装置包括：提取电路网列表的电路网列表提取部，基于提取的网表执行电路模拟的电路模拟执行部，有限的 判断有无阻抗的存在或不存在的阻抗判定部，通过测量有限阻抗来判断浮动误差端子的存在或不存在的浮动误差终端判定部;真浮动误差终端判定部，将P沟道型晶体管 和N沟道型晶体管连接到电路的端子，其中判断出存在浮动误差端子并且计算端子处的电位变化，并将另一个P沟道型晶体管和N沟道型晶体管加到 终端，并计算终端的电位变化，以及输出判断输出部 浮动误差终端判断部分的结果和真实浮动错误终端判断部分的判断结果。

公开(公告)号：US07739634B2

公开(公告)日：2010-06-15

申请号：US11742287

申请日：2007-04-30

申请人： Shigeo Ohshima ,  Kiminobu Suzuki

发明人： Shigeo Ohshima ,  Kiminobu Suzuki

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The verification equipment of a semiconductor integrated circuit in the present invention is included with a circuit net list extraction section that extracts the net list of a circuit, a circuit simulation execution section that executes a circuit simulation, based on the extracted net list, a finite impedance judgment section that judges existence or nonexistence of finite impedances, a floating error terminal judgment section that judges existence or nonexistence of floating error terminals by measuring finite impedances, a true floating error terminal judgment section that adds any one of a P channel-type transistor and an N channel-type transistor to terminals of the circuit where it is judged that there are floating error terminals and calculates changes in potential at the terminals and adds the other of the P channel-type transistor and the N channel-type transistor to the terminals and calculates changes in potential at the terminals, and an output section that outputs a judgment result of the floating error terminal judgment section and a judgment result of the true floating error terminal judgment section.

摘要翻译： 本发明的半导体集成电路的验证装置包括：提取电路网列表的电路网列表提取部，基于提取的网表执行电路模拟的电路模拟执行部，有限的 判断有无阻抗的存在或不存在的阻抗判定部，通过测量有限阻抗来判断浮动误差端子的存在或不存在的浮动误差终端判定部;真浮动误差终端判定部，将P沟道型晶体管 和N沟道型晶体管连接到电路的端子，其中判断出存在浮动误差端子并且计算端子处的电位变化，并将另一个P沟道型晶体管和N沟道型晶体管加到 终端，并计算终端的电位变化，以及输出判断输出部 浮动误差终端判断部分的结果和真实浮动错误终端判断部分的判断结果。

公开(公告)号：US20080141196A1

公开(公告)日：2008-06-12

申请号：US11945537

申请日：2007-11-27

申请人： Shigeo Ohshima ,  Kiminobu Suzuki ,  Kazuhiro Yamada ,  Takamichi Arizono

发明人： Shigeo Ohshima ,  Kiminobu Suzuki ,  Kazuhiro Yamada ,  Takamichi Arizono

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logic circuit, a resistance information extraction section which extracts resistance information of a wire from the layout-data, a circuit simulation execution section which executes a circuit simulation, an identification section of current direction which identifies a direction of a current in the wire based on the resistance information of a wire and an execution result of the circuit simulation, a verification section which verifies whether layout-data of the wire breaks a design rule, the design rule being extracted from the information of the specifications of a semiconductor integrated circuit and the verification section generates this verification result, and a data output section which outputs the layout-data.

摘要翻译： 布局数据生成装置包括逻辑电路设计部，其基于半导体集成电路的规格信息设计逻辑电路，基于逻辑电路生成布局数据的布局数据生成部，电阻信息提取 从布局数据中提取线的电阻信息的部分，执行电路仿真的电路仿真执行部，基于电线的电阻信息识别线中的电流方向的电流方向的识别部，以及 电路仿真的执行结果，验证电线的布局数据是否断开设计规则的验证部分，从半导体集成电路的规格信息中提取设计规则，并且验证部分生成该验证结果， 以及输出布局数据的数据输出部。

公开(公告)号：US07823105B2

公开(公告)日：2010-10-26

申请号：US11945537

申请日：2007-11-27

申请人： Shigeo Ohshima ,  Kiminobu Suzuki ,  Kazuhiro Yamada ,  Takamichi Arizono

发明人： Shigeo Ohshima ,  Kiminobu Suzuki ,  Kazuhiro Yamada ,  Takamichi Arizono

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logic circuit, a resistance information extraction section which extracts resistance information of a wire from the layout-data, a circuit simulation execution section which executes a circuit simulation, an identification section of current direction which identifies a direction of a current in the wire based on the resistance information of a wire and an execution result of the circuit simulation, a verification section which verifies whether layout-data of the wire breaks a design rule, the design rule being extracted from the information of the specifications of a semiconductor integrated circuit and the verification section generates this verification result, and a data output section which outputs the layout-data.

摘要翻译： 布局数据生成装置包括逻辑电路设计部，其基于半导体集成电路的规格信息设计逻辑电路，基于逻辑电路生成布局数据的布局数据生成部，电阻信息提取 从布局数据中提取线的电阻信息的部分，执行电路仿真的电路仿真执行部，基于电线的电阻信息识别线中的电流方向的电流方向的识别部，以及 电路仿真的执行结果，验证电线的布局数据是否断开设计规则的验证部分，从半导体集成电路的规格信息中提取设计规则，并且验证部分生成该验证结果， 以及输出布局数据的数据输出部。