-
公开(公告)号：US20110208904A1
公开(公告)日：2011-08-25
申请号：US13099720
申请日：2011-05-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G06F12/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞格的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并且具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
-
公开(公告)号：US20100080058A1
公开(公告)日：2010-04-01
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
-
公开(公告)号：US20080089146A1
公开(公告)日：2008-04-17
申请号：US11869144
申请日：2007-10-09
申请人： Masamichi FUJITO , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi FUJITO , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞格的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并且具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
-
公开(公告)号：US08144518B2
公开(公告)日：2012-03-27
申请号：US13099720
申请日：2011-05-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
-
公开(公告)号：US07646642B2
公开(公告)日：2010-01-12
申请号：US11869144
申请日：2007-10-09
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
-
公开(公告)号：US07957195B2
公开(公告)日：2011-06-07
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
-
公开(公告)号：US08802458B2
公开(公告)日：2014-08-12
申请号：US13348501
申请日：2012-01-11
IPC分类号： H01L33/36
CPC分类号： H01S5/4031 , H01S5/02276 , H01S5/0425 , H01S5/22 , H01S2301/14 , H01S2301/176
摘要： A laser diode capable of independently driving each ridge section, and inhibiting rotation of a polarization angle resulting from a stress applied to the ridge section without lowering reliability and a method of manufacturing the same are provided. A laser diode includes: three or more strip-like ridge sections in parallel with each other with a strip-like trench in between, including at least a lower cladding layer, an active layer, and an upper cladding layer in this order; an upper electrode on a top face of each ridge section, being electrically connected to the upper cladding layer; a wiring layer electrically connected to the upper electrode, in the air at least over the trench; and a pad electrode in a region different from regions of both the ridge section and the trench, being electrically connected to the upper electrode through the wiring layer.
摘要翻译： 提供能够独立地驱动每个脊部的激光二极管，并且抑制由于施加到脊部的应力而导致的偏振角的旋转而不降低可靠性及其制造方法。 激光二极管包括：三个或更多个带状脊部部分，其间具有彼此平行的带状沟槽，其间依次包括至少下包层，有源层和上包层; 每个脊部的顶面上的上电极，与上包层电连接; 在空气中至少在沟槽上方电连接到上电极的布线层; 以及与脊部和沟槽的区域不同的区域中的焊盘电极，通过布线层与上部电极电连接。
-
公开(公告)号：US07791122B2
公开(公告)日：2010-09-07
申请号：US12396130
申请日：2009-03-02
申请人： Takahiro Yokoyama
发明人： Takahiro Yokoyama
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： G11C11/4125 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , Y10S257/903 , Y10S257/904
摘要： In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistors, first and second load MOS transistors and first and second access MOS transistors, two capacitors are arranged spaced apart from each other on embedded interconnections to be storage nodes, with lower and upper cell plates cross-coupled to each other.
摘要翻译： 在具有包括第一和第二驱动器MOS晶体管的横向型单元（具有在字线延伸方向上并排布置并且在字线方向上比在位线方向上更长的三个分隔阱的存储单元）的完整CMOS SRAM中， 和第二负载MOS晶体管以及第一和第二存取MOS晶体管，两个电容器在嵌入式互连上彼此间隔布置成为存储节点，其中下单元板和上单元板彼此交叉耦合。
-
公开(公告)号：US07064398B2
公开(公告)日：2006-06-20
申请号：US11016905
申请日：2004-12-21
申请人： Takahiro Yokoyama
发明人： Takahiro Yokoyama
IPC分类号： H01L29/76 , H01L29/94 , H01L31/62 , H01L31/113 , H01L31/119
CPC分类号： G11C11/4125 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , Y10S257/903 , Y10S257/904
摘要： In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistors, first and second load MOS transistors and first and second access MOS transistors, two capacitors are arranged spaced apart from each other on embedded interconnections to be storage nodes, with lower and upper cell plates cross-coupled to each other.
-
公开(公告)号：US5982236A
公开(公告)日：1999-11-09
申请号：US009241
申请日：1998-01-20
申请人： Osamu Ishikawa , Takahiro Yokoyama , Taketo Kunihisa , Junji Ito , Masaaki Nishijima , Shinji Yamamoto
发明人： Osamu Ishikawa , Takahiro Yokoyama , Taketo Kunihisa , Junji Ito , Masaaki Nishijima , Shinji Yamamoto
CPC分类号： H03F3/601 , H03F1/0261
摘要： A high-frequency power amplifier comprises a transistor for high-frequency power which operates and whose current-voltage characteristics greatly change when positive voltage is supplied on its input terminal, an input bias circuit, an output bias circuit, an input impedance matching circuit, an output impedance matching circuit, and a positive voltage generation circuit. The positive voltage generation circuit comprises a detection circuit which detects part of the high-frequency power which is entered to or outputted from the transistor for high-frequency power, a rectification circuit which rectifies the part of the high-frequency power outputted from the detection circuit and outputs pulsating positive voltage, and a smoothing circuit which smoothes the pulsating positive voltage outputted from the rectification circuit and outputs positive voltage. The positive voltage generation circuit outputs positive voltage which increases or decreases in accordance with an increase or decrease in the detected part of the high-frequency power to the input terminal of the input bias circuit, without intervention of a direct-current power supply.
摘要翻译： 高频功率放大器包括用于高频功率的晶体管，其工作时的电流电压特性在其输入端子上提供正电压，输入偏置电路，输出偏置电路，输入阻抗匹配电路， 输出阻抗匹配电路和正电压发生电路。 正电压发生电路包括：检测电路，其检测输入到高频电源的晶体管或从高频电源的晶体管输出的高频电力的一部分;整流电路，其对检测出的部分高频电力进行整流; 电路和输出脉动正电压，以及平滑电路，其使从整流电路输出的脉动正电压平滑并输出正电压。 正电压发生电路根据高频电源的检测部分对输入偏置电路的输入端子的增加或减少而输出正电压，而不需要直流电源的干预。
-
-
-
-
-
-
-
-
-
搜索结果
36 条记录 (耗时 0.043 秒)