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1.发明授权Output control circuit for reducing through current in CMOS output buffer 失效用于减少CMOS输出缓冲器中的直流电流的输出控制电路
公开(公告)号：US5034629A
公开(公告)日：1991-07-23
申请号：US552855
申请日：1990-07-16
IPC分类号： H03K17/16 , G11C11/409 , H03K19/003 , H03K19/0185 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/00361 , H03K19/09429 , H03K19/0948
摘要： In an output circuit for use in a semiconductor IC comprising a CMOS transistors constituting an output buffer, a transfer gate of CMOS structure is connected between the gates of the CMOS transistors as a resistive element. The transfer gate reduces the changes in the gate potentials of output transistors, which occur when logic inputs are supplied to the gates of the output control transistors. Hence, the deformation of the output waveform, which has resulted from the through currents flowing through the output transistors, is minimized.
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公开(公告)号：US5402005A
公开(公告)日：1995-03-28
申请号：US291037
申请日：1994-08-15
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L23/48 , H01L29/46 , H01L29/54 , H01L29/62
CPC分类号： H01L23/528 , H01L23/5226 , H01L2924/0002
摘要： At least one slit having a predetermined shape is formed around a contact region of a lower wiring layer formed on a substrate, and an insulating portion formed integrally with an insulating layer is embedded in this slit. This insulating layer is formed on the lower wiring layer and has a contact hole located at a position corresponding to the contact region. Since the insulating portion as a rectangular projecting portion projects into the slit downwardly from the rigid insulating layer, positional errors caused by thermal expansion of the lower wiring layer in annealing of the upper wiring layer can be suppressed, and an abnormal geometry such as a projection on the upper wiring layer can be prevented. In addition, a semiconductor device free from interwiring short-circuiting and excellent in flatness can be obtained.
摘要翻译： 在形成在基板上的下布线层的接触区域周围形成具有预定形状的至少一个狭缝，并且与该绝缘层一体形成的绝缘部分嵌入该狭缝中。 该绝缘层形成在下布线层上，并具有位于与接触区域对应的位置的接触孔。 由于作为矩形突起部分的绝缘部分从刚性绝缘层向下突出到狭缝中，所以可以抑制由上部布线层的退火中的下部布线层的热膨胀引起的位置误差，以及诸如突起 可以防止在上部布线层上。 此外，可以获得没有相互连接短路并且具有优异的平坦度的半导体器件。
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公开(公告)号：US5107137A
公开(公告)日：1992-04-21
申请号：US576940
申请日：1990-09-04
IPC分类号： H03K3/037 , H03K3/356 , H03K3/3562 , H03K3/3565
CPC分类号： H03K3/35625 , H03K3/0372 , H03K3/3565
摘要： In a master-slave type flip-flop circuit comprising a master output holding circuit of the master stage circuit, the threshold value of the input circuit of the slave stage circuit has a hysteresis characteristic in which the high level threshold value is set to a higher value than the threshold value of the master output holding circuit and the low level threshold value is set to a lower value than the threshold value of the master output holding circuit. Due to the feature, a phenomenon is prevented in which the output is once inverted and then again inverted in the metastable state.
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公开(公告)号：US4821084A
公开(公告)日：1989-04-11
申请号：US5668
申请日：1987-01-21
IPC分类号： H01L29/78 , H01L23/528 , H01L27/118 , H01L29/417 , H01L29/423 , H01L29/94 , H01L27/10
CPC分类号： H01L23/528 , H01L27/11898 , H01L29/41758 , H01L2924/0002
摘要： Extension directions of source electrode layer and a drain electrode are parallel to rows or columns of an array of alternately arranged source regions and drain regions, thereby forming widths of source and drain electrode layers wider than those of a conventional transistor to obtain a large mutual conductance.
摘要翻译： 源极电极层和漏电极的延伸方向平行于交替排列的源极区域和漏极区域的阵列的行或列，从而形成比常规晶体管宽的源极和漏极电极层的宽度以获得大的互导 。
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公开(公告)号：US5389834A
公开(公告)日：1995-02-14
申请号：US975482
申请日：1992-11-12
IPC分类号： H03K17/687 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0948
CPC分类号： H03K19/01721 , H03K19/00361
摘要： This invention discloses a signal output circuit including DC and AC buffers having output nodes commonly connected to a signal output terminal, and an AC buffer control circuit for driving the AC buffer when an output from the DC buffer is changed and for controlling an output from the AC buffer in a high-impedance state when the output from the DC buffer is stationary.
摘要翻译： 本发明公开了一种信号输出电路，包括具有共同连接到信号输出端子的输出节点的DC和AC缓冲器，以及用于在DC缓冲器的输出改变时用于驱动AC缓冲器的AC缓冲器控制电路， 交流缓冲器在高阻抗状态时，直流缓冲器的输出是静止的。
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公开(公告)号：US06828846B2
公开(公告)日：2004-12-07
申请号：US10300807
申请日：2002-11-21
IPC分类号： H03K1762
CPC分类号： H03K17/6874 , H03K17/165 , H03K17/6872 , H03K2217/0018
摘要： An analog switch circuit includes: an analog switch composed of a first P-channel MOS transistor and a first N-channel transistor, a gate of which receives a control signal; a comparison circuit comparing potentials of a first input-output-terminal and a second input-output terminal, and conveying a higher potential to a well where the first P-channel MOS transistor is formed; a first potential conveying circuit conveying a potential of the well where the first P-channel MOS transistor is formed to a gate of the first P-channel MOS transistor when the analog switch is in the OFF state; a second potential conveying circuit operating on the basis of a control signal to convey the potential of the well where the first P-channel MOS transistor is formed to the gate of the first P-channel MOS transistor to turn off the first P-channel MOS transistor; and a third potential conveying section operating on the basis of the control signal to turn on the first P-channel MOS transistor.
摘要翻译： 模拟开关电路包括：由第一P沟道MOS晶体管和第一N沟道晶体管构成的模拟开关，其栅极接收控制信号; 比较电路，比较第一输入 - 输出端和第二输入 - 输出端的电位，并向形成第一P沟道MOS晶体管的阱传送更高的电位; 当所述模拟开关处于截止状态时，将形成所述第一P沟道MOS晶体管的阱的电势传送到所述第一P沟道MOS晶体管的栅极的第一潜在输送电路; 基于控制信号操作的第二电位传送电路，以将形成有第一P沟道MOS晶体管的阱的电位传送到第一P沟道MOS晶体管的栅极，以将第一P沟道MOS 晶体管 以及第三电位输送部，其基于所述控制信号进行工作，以导通所述第一P沟道MOS晶体管。
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公开(公告)号：US5831449A
公开(公告)日：1998-11-03
申请号：US844663
申请日：1997-04-21
IPC分类号： G06F3/00 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/09429 , H03K19/00315 , H03K19/018521
摘要： An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.
摘要翻译： 一种输出电路，包括输出级和控制信号发生器。 输出级由第一P沟道MOS晶体管和N沟道MOS晶体管构成。 控制信号发生器产生用于驱动MOS晶体管的栅极的信号，它包括与非门，或非门NOR1和反相器INV1。 输出级的第一P沟道MOS晶体管有一个源极和一个背电极，它们是以电位方式隔离的。 提供了第二P沟道MOS晶体管，其源极 - 漏极路径连接在并入输出级的第一P沟道MOS晶体管的背栅极和栅极之间。
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公开(公告)号：US5739702A
公开(公告)日：1998-04-14
申请号：US704995
申请日：1996-08-29
IPC分类号： H03K3/356 , H03K19/0175
CPC分类号： H03K3/356104
摘要： The bus hold circuit comprises: an input stage inverter (IN1) connected between a first supply voltage (Vcc) terminal and a second supply voltage (Vss) terminal and including: a first P-channel transistor (P1); and a first N-channel transistor (N1) connected in series to the first P-channel transistor, a gate of the first P-channel transistor and a gate of the first N-channel transistor being connected in common to a bus line (INA); and an output stage inverter (IN2) also connected between the first supply voltage (Vcc) terminal and the second supply voltage (Vss) terminal and including: a second P-channel transistor (P4); a third P-channel transistor (P2) connected in series to the second P-channel transistor; and a second N-channel transistor (N2) connected in series to the third P-channel transistor, a gate of the second P-channel transistor (P4) being connected to the bus line (Lout), a gate of the third P-channel transistor (P2) and a gate of the second N-channel transistor (N2) being connected in common to a drain of the first P-channel transistor (P1) and a drain of the first N-channel transistor (N1), a drain of the third P-channel transistor (P2) and a drain of the second N-channel transistor (N2) being connected in common to the bus line (Lout). In particular, back gates (i.e., the N-type well) of the first second and third P-channel transistors (P1, P4 and P2) are all connected to a source of the P-channel transistor (P2), respectively. Therefore, it is possible to prevent unnecessary current from flowing to the supply voltage terminal of the bus hold circuit, even if an output circuit supplied with a supply voltage different from that of the bus hold circuit is connected to the bus line.
摘要翻译： 总线保持电路包括：连接在第一电源电压（Vcc）端子和第二电源电压（Vss）端子之间的输入级反相器（IN1），包括：第一P沟道晶体管（P1）; 和与第一P沟道晶体管串联连接的第一N沟道晶体管（N1），第一P沟道晶体管的栅极和第一N沟道晶体管的栅极共同连接到总线（INA ）; 以及还连接在第一电源电压（Vcc）端子和第二电源电压（Vss）端子之间的输出级反相器（IN2），包括：第二P沟道晶体管（P4）; 与第二P沟道晶体管串联连接的第三P沟道晶体管（P2）; 和与第三P沟道晶体管串联连接的第二N沟道晶体管（N2），第二P沟道晶体管（P4）的栅极连接到总线（Lout），第三P沟道晶体管的栅极 沟道晶体管（P2）和第二N沟道晶体管（N2）的栅极共同连接到第一P沟道晶体管（P1）的漏极和第一N沟道晶体管（N1）的漏极， 第三P沟道晶体管（P2）的漏极和第二N沟道晶体管（N2）的漏极共同连接到总线（Lout）。 特别地，第一第二和第三P沟道晶体管（P1，P4和P2）的背栅极（即N型阱）分别连接到P沟道晶体管（P2）的源极。 因此，即使提供了与总线保持电路不同的电源电压的输出电路连接到总线线路，也可以防止不必要的电流流向总线保持电路的电源电压端子。
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公开(公告)号：US5493233A
公开(公告)日：1996-02-20
申请号：US353397
申请日：1994-12-02
IPC分类号： H01L27/04 , H01L21/822 , H03K19/003 , H03K19/0175 , H03K17/16
CPC分类号： H03K19/00315
摘要： A transistor circuit apparatus comprises a MOS transistor to be improved, for preventing an avalanche breakdown, the MOS transistor being connected in a channel conductor path provided between one of power supply terminals and a terminal of an output, a separate circuit connected to the output terminal and driven by a voltage from a separate power supply, and a pull-down unit including a second transistor connected between one of said power supply terminals and a back gate of the MOS transistor, the second transistor being turned on with an output node of the separate circuit used as power supply when the MOS transistor remains at a ground potential level with no power supply potential supplied, thereby pulling down the potential level of a back gate node of the MOS transistor to the level of one of the power supply terminals.
摘要翻译： 一种晶体管电路装置，其特征在于，具有改善的MOS晶体管，用于防止雪崩击穿，MOS晶体管连接在设置在电源端子和输出端子之间的沟道导体路径中，与输出端子连接的分立电路 并且由来自单独的电源的电压驱动，以及下拉单元，其包括连接在所述电源端子之一和所述MOS晶体管的背栅之间的第二晶体管，所述第二晶体管由所述第二晶体管的输出节点导通， 当MOS晶体管保持在没有电源电位的接地电位电平时用作电源的单独电路，从而将MOS晶体管的背栅极节点的电位下降到电源端子之一的电平。
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公开(公告)号：US6097217A
公开(公告)日：2000-08-01
申请号：US210761
申请日：1998-12-14
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/00315
摘要： Either the power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.
摘要翻译： 电源电位或接地电位通过开关施加到电源节点。 当在电源节点连接到接地电位节点的同时将高于接地电位的电位施加到输出端子时，结合在输出部分中的第一PMOS晶体管的背栅极的电位根据 由于设置在第一PMOS晶体管的漏极和背栅之间的pn结，输出端子的电位。 此时，源极 - 漏极路径连接在第一PMOS晶体管的背栅极和栅极之间的第二PMOS晶体管导通，由此第一PMOS晶体管的背栅极的电位被传送到其栅极。
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