摘要:
A protection circuit of a digital amplifier includes a DC voltage detection circuit for detecting a DC voltage occurring in a loudspeaker output terminal; a control circuit for performing protection operation when the DC voltage detection circuit outputs a detection signal; and a midpoint potential detection circuit for detecting midpoint potential shift between a positive power supply voltage and a negative power supply voltage. Output of the midpoint potential detection circuit is connected to input of the DC voltage detection circuit and when the midpoint potential shift is detected, the DC voltage detection circuit outputs a detection signal.
摘要:
A protection circuit of a digital amplifier includes a DC voltage detection circuit for detecting a DC voltage occurring in a loudspeaker output terminal; a control circuit for performing protection operation when the DC voltage detection circuit outputs a detection signal; and a midpoint potential detection circuit for detecting midpoint potential shift between a positive power supply voltage and a negative power supply voltage. Output of the midpoint potential detection circuit is connected to input of the DC voltage detection circuit and when the midpoint potential shift is detected, the DC voltage detection circuit outputs a detection signal.
摘要:
An amplification system of the invention can decrease power consumption in a power amplification section if the power amplification section need not be used. The power consumption in the power amplification section can be decreased by shutting off power feed into a voltage amplification stage by a power control section, and the power feed state into a power amplification stage from a power supply section is not changed. Thus, power feed into the voltage amplification stage of the circuit wherein a large current does not flow needs only to be controlled using limiter means also used for a different application, so that the power consumption of the power amplification section can be decreased without the need for enlarging the circuit scale, with saved space, and simply.
摘要:
A complementary signal generating circuit (301) generates first complementary signals (S1, S2) from a PWM signal. A signal converting circuit (302) converts the first complementary signals to second complementary signals (S3, S4 or S5, S6) having a voltage component based on a negative power supply (VPP−). Among the second-complementary signals, the signals (S3, S4) are supplied to a driving circuit (305), and the signals (S5, S6) are supplied to a current driving circuit (303). In response to the signals (S5, S6), the current driving circuit outputs third complementary signals (H3, H4) having a current component that is directed toward the negative power supply (VPP−), to a driving circuit (304). As a result, the driving circuits (304, 305) complementarily drive power-MOS transistors (401, 402).
摘要:
An operational amplifier has a differential amplifier stage comprising a pair of first PMOS transistors for inputting signals, which are arranged between a positive voltage supply coupled with a first constant current source and a negative voltage supply, wherein second PMOS transistors of a high voltage resistant type, gates of which are biased to a prescribed voltage, are arranged on current paths lying between the first PMOS transistors and the negative voltage supply together with load resistors. Herein, each of drain voltages of the first PMOS transistors is limited to a certain value that is higher than the prescribed voltage by a gate threshold voltage. Therefore, even when the first PMOS transistors are configured of a normal voltage resistant type, it is possible to reliably prevent voltages applied to the first PMOS transistors from exceeding breakdown voltages thereof, thus avoiding unnecessary reduction of an S/N ratio.
摘要:
Differential integrator circuit integrates a differential between a difference between a signal supplied from a first signal source and a feedback signal of amplifier output and a difference between a signal supplied from a second signal source and a feedback signal of the amplifier output. The signal supplied from the second signal source is opposite in phase from the signal supplied from the first signal source. Thus, the integrator circuit outputs two integrated signals of different polarities. Comparator compares the two integrated signals from the integrator circuit to thereby output a PWM signal. First driver circuit amplifies the PWM signal and outputs the amplified PWM signal with inverted phase, and a second driver circuit amplifies the PWM signal and outputs the amplified PWM signal with noninverted phase. First switching circuit is driven by the output of the first driver circuit, while a second switching circuit is driven by the output of the second driver circuit.
摘要:
A highly efficient analog-to-digital (A/D) converter circuit that converts an external analog signal sequentially generated from an external analog signal source into an n-bit digital data signal (n is an integer equal to or more than two) includes a digital-to-analog (D/A) converter circuit that converts an n-bit digital data signal into an analog signal and outputting the analog signal from a first output terminal, a comparator that compares a signal level of an external analog signal supplied from an external device with a signal level of the analog signal outputted from the first output terminal, and a digital integrator circuit that digitally integrates a 1-bit digital data signal outputted from the comparator and thereby producing an n-bit digital data signal.
摘要:
A class D amplifier includes: an integrating circuit (1) which integrates an input signal; a flash A/D converter (2) which A/D converts an output signal of the integrating circuit; a waveform converting circuit (3) which produces a PWM signal based on an output of the flash A/D converter; a switching circuit which is includes a pair of MOS transistors (5, 6) connected between a first power source and a second power source, the junction point P of the pair of MOS transistors being connected to a loudspeaker (51); a driving circuit (4) which drives the pair of MOS transistors on the basis of the PWM signal; and a feedback resistor (RNF) which is connected between the junction point P and the input side of the integrating circuit, and negatively feeds back the output signal of the amplifier.
摘要:
An A/D conversion apparatus is provided, which is capable of securing a wide dynamic range of A/D conversion with a simple construction through suitably switching the input gain of the input analog signal between predetermined levels. An input gain control device controls gain of an input signal based on a control signal. A &Dgr;&Sgr; modulator carries out oversampling of the input signal having the gain thereof controlled by the input gain control device to convert the input signal to data of one bit. A detecting device detects a peak value of the input signal based on the data of one bit. A gain control device generates the control signal based on the peak value detected by the detecting device in a manner such that the input signal having the gain thereof controlled falls within a predetermined range. To effectively reduce noise of the output digital signal while securing a wide dynamic range of A/D conversion, the &Dgr;&Sgr; modulator may also control the gain of the input signal based on the control signal to a predetermined value (1/A) smaller than 1, and the decimation circuit may have a gain of a second predetermined value (A) for compensating for the gain of the input signal controlled to the predetermined value (1/A).
摘要:
An analog-digital converter comprises a .DELTA. .SIGMA. modulator, a digital filter, a high-pass filter and a multiplier which are connected in series. Analog input is converted into serial-bit strings by the .DELTA. .SIGMA. modulator, for which gain `1/A` is set. The digital filter extracts low-frequency components, corresponding to the analog input, from the serial-bit strings, so the low-frequency components are converted into parallel-bit digital data. The high-pass filter removes DC offset component from output of the digital filter; and then, output thereof is multiplied by scaling gain `A` by the multiplier so that digital output is produced. The .DELTA. .SIGMA. modulator comprises at least three switched-capacitor integrators and a one-bit quantizer, which are connected in series, as well as a one-sample delay circuit. One-bit output, produced by the one-bit quantizer, is delayed by the one-sample delay circuit, whose output is delivered to each switched-capacitor integrator. Each switched-capacitor integrator is configured using a CMOS differential amplifier which is configured by a CMOS operational amplifier and at least one amplitude-limiting circuit. The amplitude-limiting circuit is configured by two PMOS transistors and two NMOS transistors which are connected in parallel in a diode-connection manner; and this circuit is provided to limit amplitude in output of the CMOS differential amplifier by stabilizing its operating point.