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公开(公告)号：US08350791B2
公开(公告)日：2013-01-08
申请号：US12003555
申请日：2007-12-28
IPC分类号： G09G3/36
CPC分类号： H04N5/23293 , H04N5/232 , H04N5/23241
摘要： In displaying image data received from a camera module on a display device such as a view finder, image data having a size suited for display from an image size conversion circuit is displayed via line memories included in a signal-for-display generation circuit. Vertical synchronization in an image data storage including these line memories is established by initializing a reading address in accordance with a frame head pixel indication and a reading completion indication of one line in the line memories. It is possible to reduce power consumption of an image display system for displaying an image of a imaging subject.
摘要翻译： 在显示诸如取景器的显示装置上显示从相机模块接收到的图像数据时，通过包括在显示信号生成电路中的线路存储器显示具有适合于从图像尺寸转换电路显示的尺寸的图像数据。 通过根据帧头像素指示和行存储器中的一行的读取完成指示初始化读取地址来建立包括这些行存储器的图像数据存储器中的垂直同步。 可以降低用于显示成像对象的图像的图像显示系统的功耗。
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公开(公告)号：US20080165268A1
公开(公告)日：2008-07-10
申请号：US12003555
申请日：2007-12-28
IPC分类号： H04N5/225
CPC分类号： H04N5/23293 , H04N5/232 , H04N5/23241
摘要： In displaying image data received from a camera module on a display device such as a view finder, image data having a size suited for display from an image size conversion circuit is displayed via line memories included in a signal-for-display generation circuit. Vertical synchronization in an image data storage including these line memories is established by initializing a reading address in accordance with a frame head pixel indication and a reading completion indication of one line in the line memories. It is possible to reduce power consumption of an image display system for displaying an image of a imaging subject.
摘要翻译： 在显示诸如取景器的显示装置上显示从相机模块接收到的图像数据时，通过包括在显示信号生成电路中的线路存储器显示具有适合于从图像尺寸转换电路显示的尺寸的图像数据。 通过根据帧头像素指示和行存储器中的一行的读取完成指示初始化读取地址来建立包括这些行存储器的图像数据存储器中的垂直同步。 可以减少用于显示成像对象的图像的图像显示系统的功耗。
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公开(公告)号：US3957474A
公开(公告)日：1976-05-18
申请号：US569113
申请日：1975-04-17
申请人： Soichi Kobayashi , Tatsuo Izawa
发明人： Soichi Kobayashi , Tatsuo Izawa
IPC分类号： C03B37/018 , A63F3/04 , C03B37/00 , C03B37/014 , C03C3/06 , C03C13/04 , G02B6/00 , C03C25/02 , C03C13/00
CPC分类号： C03B37/01413 , C03B37/0142 , C03B37/0148 , C03C13/045 , C03C3/06 , C03B2207/81 , C03B2207/85 , C03B2207/87 , C03C2201/30 , C03C2201/31 , C03C2201/32 , C03C2201/42 , C03C2203/44
摘要： A method for manufacturing a glass core rod and a cladding layer clothing the glass core rod applied successively or continuously by using a carbon dioxide gas laser. A refractory mandrel is heated by means of carbon dioxide gas laser irradiation and a mixed gas of oxygen and pure silicon tetrachloride vapor and a dopant compound vapor is ejected to the refractory mandrel so as to deposit silicon oxide and oxide of the dopant compound on the mandrel and to form a glass core by fusing it. Further heating is applied by irradiation by the carbon dioxide laser beam on the glass core and a mixed gas oxygen and pure silicon tetrachloride vapor and a dopant compound vapor or of oxygen gas and pure silicon tetrachloride vapor to deposit silicon oxide and oxide of the dopant compound or silicon oxide on the glass core to form a cladding layer of fused silica or fused silica containing the dopant. The preform thus formed by the glass core and the cladding is heated above the softening temperature of the preform so as to spin to form an optical fibre. The method uses laser beam heating which results in less degree of contaminating impurity and water content which might cause absorption and scattering of light also to manufacture an optical fiber having less variation at the boundary of the glass core and the cladding layer.
摘要翻译： 一种用于制造玻璃芯棒和包层的方法，其通过使用二氧化碳气体激光器连续或连续地施加玻璃芯棒。 通过二氧化碳气体激光照射加热耐火心轴，并将氧和纯四氯化硅蒸汽和掺杂剂化合物蒸汽的混合气体喷射到耐火材料心轴上，以将氧化硅和掺杂剂化合物的氧化物沉积在心轴上 并通过熔化形成玻璃芯。 通过二氧化碳激光束照射在玻璃芯和混合气体氧气和纯四氯化硅蒸气以及掺杂剂化合物蒸气或氧气和纯四氯化硅蒸汽上进行进一步加热，以沉积氧化硅和掺杂剂化合物的氧化物 或硅氧化物，以形成包含掺杂剂的熔融二氧化硅或熔融二氧化硅的包覆层。 将由玻璃芯和包层形成的预制件加热到预成型体的软化温度以上以旋转形成光纤。 该方法使用激光束加热，其导致较少污染杂质和水分含量，这可能导致光的吸收和散射，也可以制造在玻璃芯和包层的边界处具有较小变化的光纤。
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公开(公告)号：US09529402B2
公开(公告)日：2016-12-27
申请号：US13818379
申请日：2010-09-02
申请人： Soichi Kobayashi , Akira Oizumi , Yoshihiko Yasu , Hiromi Notani
发明人： Soichi Kobayashi , Akira Oizumi , Yoshihiko Yasu , Hiromi Notani
CPC分类号： G06F1/3287 , G05F1/56 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F1/3296 , G11C5/147 , Y02D10/126 , Y02D10/128 , Y02D10/172 , Y02D50/20
摘要： A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.
摘要翻译： 降压单元降低外部电源电压Vcc。 偏置电流控制电路控制流过连接输出节点和地的辅助路径的偏置电流的大小。 在将包含中央处理单元的负载电路消耗的电流量发生相对较大变化的负载电路的操作状态改变之前，系统控制器增加偏置电流的大小。
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公开(公告)号：US20130159746A1
公开(公告)日：2013-06-20
申请号：US13818379
申请日：2010-09-02
申请人： Soichi Kobayashi , Akira Oizumi , Yoshihiko Yasu , Hiromi Notani
发明人： Soichi Kobayashi , Akira Oizumi , Yoshihiko Yasu , Hiromi Notani
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G05F1/56 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F1/3296 , G11C5/147 , Y02D10/126 , Y02D10/128 , Y02D10/172 , Y02D50/20
摘要： A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.
摘要翻译： 降压单元降低外部电源电压Vcc。 偏置电流控制电路控制流过连接输出节点和地的辅助路径的偏置电流的大小。 在将包含中央处理单元的负载电路消耗的电流量发生相对较大变化的负载电路的操作状态改变之前，系统控制器增加偏置电流的大小。
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6.发明申请公开(公告)号：US20080288836A1
公开(公告)日：2008-11-20
申请号：US12219230
申请日：2008-07-17
IPC分类号： G11C29/00 , G06F11/277
CPC分类号： G11C29/848 , G11C11/41 , G11C29/44
摘要： In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.
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7.发明授权公开(公告)号：US06433594B1
公开(公告)日：2002-08-13
申请号：US09794028
申请日：2001-02-28
申请人： Soichi Kobayashi
发明人： Soichi Kobayashi
IPC分类号： H03B100
CPC分类号： H03K19/0016
摘要： A signal output circuit includes a first NMOS transistor that supplies the potential of its drain as output data to an output terminal that has been pulled up to a high power source voltage. This signal output circuit includes a second NMOS transistor having input to its gate a control signal that becomes a high logical level when there is no power supplied, and having its drain connected to the gate of the first NMOS transistor.
摘要翻译： 信号输出电路包括将其漏极的电位作为输出数据提供给已被上拉到高电源电压的输出端的第一NMOS晶体管。 该信号输出电路包括具有向其栅极输入的控制信号的第二NMOS晶体管，当没有供电时，其漏极连接到第一NMOS晶体管的栅极，该控制信号变为高逻辑电平。
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公开(公告)号：US20130207634A1
公开(公告)日：2013-08-15
申请号：US13367883
申请日：2012-02-07
IPC分类号： G05F3/02
摘要： A semiconductor device includes a voltage generating circuit, a first switch, and a charging circuit. The voltage generating circuit generates a voltage for output and has a function to adjust a magnitude of the voltage to be generated. A first switch has a first conduction terminal and a second conduction terminal that are brought into conduction with each other in an ON state, and the first conduction terminal is connected to an output node of the voltage generating circuit via a first line. The charging circuit charges a second line connected to the second conduction terminal of the first switch.
摘要翻译： 半导体器件包括电压产生电路，第一开关和充电电路。 电压产生电路产生用于输出的电压，并且具有调整要产生的电压的大小的功能。 第一开关具有在导通状态下彼此导通的第一导通端子和第二导通端子，并且第一导通端子经由第一线路连接到电压产生电路的输出节点。 充电电路对连接到第一开关的第二导通端子的第二线路充电。
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公开(公告)号：US08860392B2
公开(公告)日：2014-10-14
申请号：US13367883
申请日：2012-02-07
摘要： A semiconductor device includes a voltage generating circuit, a first switch, and a charging circuit. The voltage generating circuit generates a voltage for output and has a function to adjust a magnitude of the voltage to be generated. A first switch has a first conduction terminal and a second conduction terminal that are brought into conduction with each other in an ON state, and the first conduction terminal is connected to an output node of the voltage generating circuit via a first line. The charging circuit charges a second line connected to the second conduction terminal of the first switch.
摘要翻译： 半导体器件包括电压产生电路，第一开关和充电电路。 电压产生电路产生用于输出的电压，并且具有调整要产生的电压的大小的功能。 第一开关具有在导通状态下彼此导通的第一导通端子和第二导通端子，并且第一导通端子经由第一线路连接到电压产生电路的输出节点。 充电电路对连接到第一开关的第二导通端子的第二线路充电。
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10.发明授权Semiconductor integrated circuit capable of testing with small scale circuit configuration 失效半导体集成电路能够以小规模电路配置进行测试公开(公告)号：US07457996B2
公开(公告)日：2008-11-25
申请号：US10632928
申请日：2003-08-04
CPC分类号： G11C29/848 , G11C11/41 , G11C29/44
摘要： In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.
摘要翻译： 在测试模式中，比较器比较每个列从连接到激活字线的每个存储单元读取的数据值与要从每个存储器单元读取的期望值。 错误寄存器根据比较器的比较结果来保存错误数据。 错误数据的每一位表示比较器对相应列的比较结果。 当相应列的比较结果始终表示相等的字线被激活时，每个位都被设置为“0”，当一个对应的列的比较结果表示差异时，将其设置为“1”。
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