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    Semiconductor device
    2.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US5055904A

    公开(公告)日：1991-10-08

    申请号：US495762

    申请日：1990-03-19

    申请人： Masataka Minami ,  Kazushige Sato ,  Atsuo Watanabe ,  Shoji Shukuri ,  Takashi Nishida ,  Takahiro Nagano

    发明人： Masataka Minami ,  Kazushige Sato ,  Atsuo Watanabe ,  Shoji Shukuri ,  Takashi Nishida ,  Takahiro Nagano

    IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L27/11

    CPC分类号： H01L27/0623 ,  H01L27/1112 ,  Y10S257/903

    摘要： A semicondcutor device and a manufacturing method thereof are disclosed in which higher integration can be achieved without increasing the total manufacturing steps. The semiconductor device includes at least two MOS transistors having the same channel types, the gate electrodes of which are constructed of polycrystal silicon layers which contain an impurity, and a bipolar transistor, the base electrode of which is constructed of a polycrystal silicon layer which contains and impurity. In particular, the respective gate electrodes of the two MOS transistors contain impurities of different conductivity types from one another.

    摘要翻译： 公开了一种半切割器件及其制造方法，其中可以在不增加总制造步骤的情况下实现更高的集成度。 半导体器件包括至少两个具有相同沟道类型的MOS晶体管，其栅电极由含有杂质的多晶硅层构成;以及双极晶体管，其基极由多晶硅层构成，该多晶硅层含有 和杂质。 特别地，两个MOS晶体管的各个栅电极彼此具有不同导电类型的杂质。

    MOS field effect transistor device with buried channel
    4.
    发明授权
    MOS field effect transistor device with buried channel 失效
    MOS场效应晶体管器件具有埋入通道

    公开(公告)号：US4916500A

    公开(公告)日：1990-04-10

    申请号：US78987

    申请日：1987-07-29

    申请人： Yoshiaki Yazawa ,  Atsuo Watanabe ,  Atsushi Hiraishi ,  Masataka Minami ,  Takahiro Nagano

    发明人： Yoshiaki Yazawa ,  Atsuo Watanabe ,  Atsushi Hiraishi ,  Masataka Minami ,  Takahiro Nagano

    IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/808

    CPC分类号： H01L29/78696 ,  H01L29/105 ,  H01L29/78 ,  H01L29/7838 ,  H01L29/808

    摘要： The present invention relates to a semiconductor device comprising a semiconductor substrate of a first conductivity type or an insulator, a source comprising an impurity layer of a second conductivity type disposed on said semiconductor substrate or said insulator, a drain comprising an impurity layer of the second conductivity type disposed on said semiconductor substrate or said insulator, an impurity layer of the first conductivity type formed between said source and said drain, a gate formed on said impurity layer of the first conductivity type via an insulation film, and an impurity layer of the second conductivity type having an impurity concentration lower than that of said source and said drain, said impurity layer of the second conductivity type being disposed between said source, said drain and said impurity layer of the first conductivity type, and said semiconductor substrate of the first conductivity type or said insulator.

    摘要翻译： 本发明涉及一种包括第一导电类型或绝缘体的半导体衬底的半导体器件，包括设置在所述半导体衬底或所述绝缘体上的第二导电类型的杂质层的源极，包括第二导电类型或绝缘体的杂质层的漏极 设置在所述半导体衬底或所述绝缘体上的导电类型，形成在所述源极和所述漏极之间的第一导电类型的杂质层，经由绝缘膜形成在所述第一导电类型的所述杂质层上的栅极和 第二导电类型的杂质浓度低于所述源极和漏极的第二导电类型，所述第二导电类型的所述杂质层设置在所述源极，所述漏极和所述第一导电类型的所述杂质层之间，所述第一导电类型的所述半导体衬底 导电类型或所述绝缘体。

    Method of fabricating bipolar transistor having high speed and MOS transistor having small size
    6.
    发明授权
    Method of fabricating bipolar transistor having high speed and MOS transistor having small size 失效
    制造具有高速度的双极晶体管的方法和具有小尺寸的MOS晶体管

    公开(公告)号：US5506156A

    公开(公告)日：1996-04-09

    申请号：US279087

    申请日：1994-07-22

    申请人： Atsuo Watanabe ,  Kazushige Sato ,  Takahiro Nagano ,  Shoji Shukuri ,  Takashi Nishida

    发明人： Atsuo Watanabe ,  Kazushige Sato ,  Takahiro Nagano ,  Shoji Shukuri ,  Takashi Nishida

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/265

    CPC分类号： H01L21/8249 ,  Y10S148/009

    摘要： A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type. Each of the semiconductor regions of the first conductive type is made up of a semiconductor layer where the impurity concentration decreases with the depth from the surface thereof, a first buried layer of the first conductive type which is formed in a semiconductor substrate and where the impurity concentration distribution in the direction of thickness has a single peak value, and a second buried layer of the first conductive type which is formed between the semiconductor layer and the first buried layer and where the impurity concentration distribution in the direction of thickness has a single peak value. The first and second buried layers are formed by the ion implantation method, after an epitaxial growth process and a field oxidation process have been completed.

    摘要翻译： 半导体器件包括多个第一导电类型的半导体区域和第二导电类型的多个半导体区域。 具有第二导电类型的沟道的AMOS晶体管形成在第一导电类型的半导体区域中，并且在第二导电类型的半导体区域中形成具有第一导电类型的沟道的双极晶体管和MOS晶体管。 第一导电类型的半导体区域由半导体层构成，其中杂质浓度随着其表面的深度而减小，第一导电类型的第一掩埋层形成在半导体衬底中，并且杂质 在厚度方向上的浓度分布具有单个峰值，并且形成在半导体层和第一掩埋层之间的第一导电类型的第二掩埋层，并且其中厚度方向上的杂质浓度分布具有单峰 值。 在外延生长处理和场氧化处理完成之后，通过离子注入法形成第一和第二掩埋层。

    Method of fabricating a semiconductor device having silicide layers for electrodes
    8.
    发明授权
    Method of fabricating a semiconductor device having silicide layers for electrodes 失效
    制造具有用于电极的硅化物层的半导体器件的方法

    公开(公告)号：US5607866A

    公开(公告)日：1997-03-04

    申请号：US458112

    申请日：1995-06-02

    申请人： Kazushige Sato ,  Atsuo Watanabe ,  Kenichi Kikushima ,  Nobuo Owada ,  Masaya Iida

    发明人： Kazushige Sato ,  Atsuo Watanabe ,  Kenichi Kikushima ,  Nobuo Owada ,  Masaya Iida

    IPC分类号： H01L21/285 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/265

    CPC分类号： H01L21/8249 ,  H01L21/28518 ,  H01L27/0635 ,  Y10S148/009

    摘要： In a method of fabricating a semiconductor device having a MISFET and/or bipolar transistor and/or a resistor formed with different surface portions of a single silicon semiconductor substrate in which a silicide layer is formed on each of source/drain regions of the MISFET and/or collector contact region and extrinsic base region of the bipolar transistor and/or contact regions of the resistor, the bipolar transistor has its emitter region formed by diffusing an impurity contained in doped polysilicon film serving as an emitter electrode of the bipolar transistor into a part of its base region. The resistor may have a resistive region formed in a surface portion of the substrate and may be covered with an insulating film and a doped polysilicon film thereon or may have a doped polysilicon film formed over a surface portion of the substrate as a resistor element. These doped polysilicon films in the resistor are films which are formed in the same step as that for the doped silicon film serving as the emitter electrode in the bipolar transistor. Each of the doped polysilicon film in the bipolar transistor and that in the resistor are covered with an insulating film before a refractory metal film is formed over a whole surface of the substrate to prevent formation of silicide films on the doped polysilicon films in the bipolar transistor and resistor.

    摘要翻译： 在制造具有MISFET和/或双极晶体管和/或形成有单晶硅半导体衬底的不同表面部分的电阻器的半导体器件的方法中，其中在MISFET的每个源极/漏极区域上形成硅化物层， /或集电极接触区域和双极性晶体管的非本征基极区域和/或电阻器的接触区域，双极晶体管的发射极区域通过将掺杂多晶硅膜中所含的杂质扩散到双极型晶体管的发射电极而形成， 其基地区的一部分。 电阻器可以具有形成在衬底的表面部分中的电阻区域，并且可以在其上覆盖绝缘膜和掺杂多晶硅膜，或者可以在衬底的表面部分上形成作为电阻器元件的掺杂多晶硅膜。 电阻器中的这些掺杂多晶硅膜是与双极晶体管中的发射极电极的掺杂硅膜相同的步骤形成的膜。 在双极晶体管的整个表面上形成耐火金属膜之前，双极晶体管中的每个掺杂多晶硅膜和电阻器中的掺杂多晶硅膜都被绝缘膜覆盖，以防止在双极晶体管中的掺杂多晶硅膜上形成硅化物膜 和电阻。