公开(公告)号：US08330254B2

公开(公告)日：2012-12-11

申请号：US12647639

申请日：2009-12-28

申请人： Masayuki Furumiya ,  Hiroaki Ohkubo ,  Fuyuki Okamoto ,  Masayuki Mizuno ,  Koichi Nose ,  Yoshihiro Nakagawa ,  Yoshio Kameda

发明人： Masayuki Furumiya ,  Hiroaki Ohkubo ,  Fuyuki Okamoto ,  Masayuki Mizuno ,  Koichi Nose ,  Yoshihiro Nakagawa ,  Yoshio Kameda

IPC分类号： H01L23/544

CPC分类号： H01L23/48 ,  G01R31/2884 ,  G01R31/3025 ,  G01R31/31721 ,  H01L22/32 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/544 ,  H01L24/06 ,  H01L2223/5446 ,  H01L2924/01029

摘要： A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.

摘要翻译： 一种半导体器件包括其半导体芯片形成区域和位于半导体芯片形成区域之间的划线区域形成的半导体晶片，设置在半导体晶片上的多个半导体芯片电路部分，设置在每个半导体芯片形成区域中的多个第一导电层 电连接到每个电路部分的半导体芯片形成区域以及跨越划线区域的一部分将第一导电层彼此电连接的第一连接部分。 外部电源或接地焊盘连接到第一导电层和第一连接部分中的任一个。 半导体器件包括连接到电路部分的通信部分，其通过电容耦合或电感耦合与外部进行通信。

公开(公告)号：US20110260747A1

公开(公告)日：2011-10-27

申请号：US13139609

申请日：2009-12-22

申请人： Yoshio Kameda ,  Yoshihiro Nakagawa ,  Koichiro Noguchi ,  Masayuki Mizuno ,  Koichi Nose

发明人： Yoshio Kameda ,  Yoshihiro Nakagawa ,  Koichiro Noguchi ,  Masayuki Mizuno ,  Koichi Nose

IPC分类号： G01R31/26 ,  G05F1/10

CPC分类号： G01R31/2884 ,  G01R31/3012

摘要： A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).

摘要翻译： 半导体器件（1）包括其上形成有多个半导体芯片形成区域（1A）的半导体晶片（11），设置在所述半导体芯片形成区域（1A）的每一个内的电路部分（12） 半导体晶片（11），设置在每个半导体芯片形成区域（1A）内并连接到电路部分（12））的控制电路部分（14），其控制供应到电路部分（12）的电力， 连接到多个控制电路部分（14）的电源线（18）和连接到多个控制电路部分（14）的参考电力线（17）。 在每个控制电路部分（14）中，基于来自参考电力线（17）的参考电压来控制从电源线（18）供应的电力的电压。

公开(公告)号：US08513970B2

公开(公告)日：2013-08-20

申请号：US13139609

申请日：2009-12-22

申请人： Yoshio Kameda ,  Yoshihiro Nakagawa ,  Koichiro Noguchi ,  Masayuki Mizuno ,  Koichi Nose

发明人： Yoshio Kameda ,  Yoshihiro Nakagawa ,  Koichiro Noguchi ,  Masayuki Mizuno ,  Koichi Nose

IPC分类号： G01R31/02

CPC分类号： G01R31/2884 ,  G01R31/3012

摘要： A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).

摘要翻译： 半导体器件（1）包括其上形成有多个半导体芯片形成区域（1A）的半导体晶片（11），设置在所述半导体芯片形成区域（1A）的每一个内的电路部分（12） 半导体晶片（11），设置在每个半导体芯片形成区域（1A）内并连接到电路部分（12））的控制电路部分（14），其控制供应到电路部分（12）的电力， 连接到多个控制电路部分（14）的电源线（18）和连接到多个控制电路部分（14）的参考电力线（17）。 在每个控制电路部分（14）中，基于来自参考电力线（17）的参考电压来控制从电源线（18）供应的电力的电压。

公开(公告)号：US20100283497A1

公开(公告)日：2010-11-11

申请号：US12810877

申请日：2008-12-16

申请人： Koichiro Noguchi ,  Yoshio Kameda ,  Koichi Nose ,  Masayuki Mizuno ,  Toshinobu Ono

发明人： Koichiro Noguchi ,  Yoshio Kameda ,  Koichi Nose ,  Masayuki Mizuno ,  Toshinobu Ono

IPC分类号： G01R31/26

CPC分类号： G01R31/31908

摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.

摘要翻译： 提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。 半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为 由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。

公开(公告)号：US08441277B2

公开(公告)日：2013-05-14

申请号：US12810877

申请日：2008-12-16

申请人： Koichiro Noguchi ,  Yoshio Kameda ,  Koichi Nose ,  Masayuki Mizuno ,  Toshinobu Ono

发明人： Koichiro Noguchi ,  Yoshio Kameda ,  Koichi Nose ,  Masayuki Mizuno ,  Toshinobu Ono

IPC分类号： G01R31/26

CPC分类号： G01R31/31908

摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.

摘要翻译： 提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。 半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为 由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。

公开(公告)号：US20120025790A1

公开(公告)日：2012-02-02

申请号：US13146806

申请日：2010-02-09

申请人： Koichiro Noguchi ,  Koichi Nose ,  Yoshihiro Nakagawa ,  Masayuki Mizuno

发明人： Koichiro Noguchi ,  Koichi Nose ,  Yoshihiro Nakagawa ,  Masayuki Mizuno

IPC分类号： G05F1/10

CPC分类号： G01R31/31721 ,  G05F1/607

摘要： An electronic circuit includes: a first power line capable of supplying power; a second power line capable of supplying power independently from the first power line; a main circuit connected to the second power line; a detector that detects the supply of power from the first power line or the second power line; and a controller connected to the first power line and the second power line, wherein the controller controls a voltage or a current supplied from the first power line and supplies the voltage or the current to the main circuit when the detector detects supply of power from the first power line.

摘要翻译： 电子电路包括：能够供电的第一电力线; 能够独立于所述第一电力线供电的第二电力线; 连接到第二电力线的主电路; 检测器，其检测来自所述第一电力线或所述第二电力线的电力供应; 以及连接到所述第一电力线和所述第二电力线的控制器，其中，所述控制器控制从所述第一电力线提供的电压或电流，并且当所述检测器检测到来自所述主电路的电力供应时，将电压或电流提供给所述主电路 第一条电力线。

公开(公告)号：US08674774B2

公开(公告)日：2014-03-18

申请号：US13394542

申请日：2010-09-01

申请人： Eisuke Saneyoshi ,  Koichi Nose ,  Masayuki Mizuno

发明人： Eisuke Saneyoshi ,  Koichi Nose ,  Masayuki Mizuno

IPC分类号： H03L7/24 ,  G01R31/28

CPC分类号： G01R31/2856 ,  G01R31/2882 ,  G01R31/2884 ,  H03K5/133

摘要： There is provided an aging diagnostic device including: a reference ring oscillator (101) that constitutes a ring oscillator using an odd-numbered plurality of logic gates constituted using a CMOS circuit; a test ring oscillator (102) that constitutes a ring oscillator using an odd-numbered plurality of logic gates having the same configuration as that of the logic gate; a load unit (104) that inputs a load signal to the test ring oscillator (102); a control unit (105) that simultaneously inputs a control signal instructing a start of oscillation of the reference ring oscillator (101) and the test ring oscillator (102) to the reference ring oscillator (101) and the test ring oscillator (102); and a comparison unit (103) that compares differences in the amount of movement of pulses within the reference ring oscillator (101) and the test ring oscillator (102), respectively, in the same time.

摘要翻译： 提供了一种老化诊断装置，包括：构成使用CMOS电路构成的奇数多个逻辑门的环形振荡器的参考环形振荡器（101） 使用具有与逻辑门相同配置的奇数多个逻辑门构成环形振荡器的测试环振荡器（102）; 负载单元（104），其向所述测试环形振荡器（102）输入负载信号; 控制单元（105），其同时将参考环形振荡器（101）和测试环形振荡器（102）的振荡开始的控制信号输入到参考环形振荡器（101）和测试环形振荡器（102）; 以及比较单元（103），其分别同时比较参考环形振荡器（101）和测试环形振荡器（102）中的脉冲的移动量的差异。

公开(公告)号：US20120161885A1

公开(公告)日：2012-06-28

申请号：US13394542

申请日：2010-09-01

申请人： Eisuke Saneyoshi ,  Koichi Nose ,  Masayuki Mizuno

发明人： Eisuke Saneyoshi ,  Koichi Nose ,  Masayuki Mizuno

IPC分类号： H03L7/24

CPC分类号： G01R31/2856 ,  G01R31/2882 ,  G01R31/2884 ,  H03K5/133

摘要： There is provided an aging diagnostic device including: a reference ring oscillator (101) that constitutes a ring oscillator using an odd-numbered plurality of logic gates constituted using a CMOS circuit; a test ring oscillator (102) that constitutes a ring oscillator using an odd-numbered plurality of logic gates having the same configuration as that of the logic gate; a load unit (104) that inputs a load signal to the test ring oscillator (102); a control unit (105) that simultaneously inputs a control signal instructing a start of oscillation of the reference ring oscillator (101) and the test ring oscillator (102) to the reference ring oscillator (101) and the test ring oscillator (102); and a comparison unit (103) that compares differences in the amount of movement of pulses within the reference ring oscillator (101) and the test ring oscillator (102), respectively, in the same time.

摘要翻译： 提供了一种老化诊断装置，包括：构成使用CMOS电路构成的奇数多个逻辑门的环形振荡器的参考环形振荡器（101） 使用具有与逻辑门相同配置的奇数多个逻辑门构成环形振荡器的测试环振荡器（102）; 负载单元（104），其向所述测试环形振荡器（102）输入负载信号; 控制单元（105），其同时将参考环形振荡器（101）和测试环形振荡器（102）的振荡开始的控制信号输入到参考环形振荡器（101）和测试环形振荡器（102）; 以及比较单元（103），其分别同时比较参考环形振荡器（101）和测试环形振荡器（102）中的脉冲的移动量的差异。

公开(公告)号：US20100052792A1

公开(公告)日：2010-03-04

申请号：US12440977

申请日：2007-09-13

申请人： Koichi Nose ,  Haruya Ishizaki ,  Masayuki Mizuno

发明人： Koichi Nose ,  Haruya Ishizaki ,  Masayuki Mizuno

IPC分类号： H03F3/68

CPC分类号： H03K4/026 ,  H03F1/0294 ,  H03F1/32 ,  H03F3/2171 ,  H03F3/2178 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/384 ,  H03K4/92

摘要： [PROBLEMS] To provide, for example, a pulse input type power amplifying apparatus that can be operated at low voltage and low power, effectively suppressing generation of harmonic component.[MEANS FOR SOLVING THE PROBLEMS] The amplifying apparatus includes at least two amplification circuits, one and other amplification circuits, composed of multiple amplifiers whose output sides are connected to each other, driven at the same frequency. The multiple amplifiers forming the one amplification circuit are configured with a first inverting amplifier M12 inputting and amplifying a reference pulse, and a second inverting amplifier M11 to which an inverted pulse formed by shifting and inverting the phase of the reference pulse is inputted. The other amplification circuit is configured with the first inverting amplifier M14 and the second inverting amplifier M13 to each of which other wide pulse with a width greater than that of the reference pulse is commonly inputted.

摘要翻译： [问题]为了提供例如能够以低电压和低功率工作的脉冲输入型功率放大装置，能有效地抑制谐波分量的产生。 解决问题的手段放大装置包括至少两个放大电路，一个和另外的放大电路，由输出侧相互连接并以相同频率驱动的多个放大器组成。 形成一个放大电路的多个放大器配置有输入和放大参考脉冲的第一反相放大器M12和输入通过移位和反相参考脉冲的相位形成的反相脉冲的第二反相放大器M11。 另一个放大电路配置有第一反相放大器M14和第二反相放大器M13，其中通常输入宽度大于参考脉冲宽度的其它宽脉冲。

公开(公告)号：US20090189596A1

公开(公告)日：2009-07-30

申请号：US12088411

申请日：2006-09-28

申请人： Koichi Nose ,  Masayuki Mizuno

发明人： Koichi Nose ,  Masayuki Mizuno

IPC分类号： G01R25/00

CPC分类号： G01R19/2509

摘要： An interpolated signal generating circuit (101) generates interpolated signals (SIG1-SIGN) of two consecutive discrete signals (SIG). N measuring circuits (501) measure interpolated signals. Since the interpolated signals are measurement targets, N-times oversampling measurement can also be performed for the discrete signals. With the oversampling measurement, the frequency spectra of the signal components of the discrete signals are maintained, and only the frequency spectrum of a noise component due to a quantization error increases to a high-frequency band, thereby reducing a noise component per unit frequency. Therefore, removing a high-frequency component from a measurement result from each measuring circuit using a low-pass filter (502) makes it possible to improve the signal-to-noise ratio of the measurement result as compared with a case in which no oversampling is performed.

摘要翻译： 内插信号生成电路（101）产生两个连续离散信号（SIG）的内插信号（SIG1-SIGN）。 N个测量电路（501）测量内插信号。 由于内插信号是测量目标，所以也可以对离散信号执行N次过采样测量。 通过过采样测量，维持离散信号的信号分量的频谱，并且只有由于量化误差引起的噪声分量的频谱增加到高频带，从而降低每单位频率的噪声分量。 因此，使用低通滤波器（502）从每个测量电路的测量结果中去除高频分量使得与没有过采样的情况相比，可以提高测量结果的信噪比 被执行。