公开(公告)号：US07282175B2

公开(公告)日：2007-10-16

申请号：US10824647

申请日：2004-04-15

申请人： Masazumi Amagai ,  Masako Watanabe ,  Kensho Murata ,  Yoshitaka Toyoda ,  Minoru Ueshima ,  Tsukasa Ohnishi ,  Takeshi Tashima ,  Daisuke Souma ,  Takahiro Roppongi ,  Hiroshi Okada

发明人： Masazumi Amagai ,  Masako Watanabe ,  Kensho Murata ,  Yoshitaka Toyoda ,  Minoru Ueshima ,  Tsukasa Ohnishi ,  Takeshi Tashima ,  Daisuke Souma ,  Takahiro Roppongi ,  Hiroshi Okada

IPC分类号： C22C13/02

CPC分类号： B23K35/262 ,  B23K2101/36

摘要： A lead-free solder includes 0.05-5 mass % of Ag, 0.01-0.5 mass % of Cu, at least one of P, Ge, Ga, Al, and Si in a total amount of 0.001-0.05 mass %, and a remainder of Sn. One or more of a transition element for improving resistance to heat cycles, a melting point lowering element such as Bi, In, or Zn, and an element for improving impact resistance such as Sb may be added.

摘要翻译： 无铅焊料包括0.05-5质量％的Ag，0.01-0.5质量％的Cu，至少一种P，Ge，Ga，Al和Si，总量为0.001-0.05质量％，余量为 的Sn。 可以添加用于提高耐热循环性的过渡元素中的一种或多种，​​诸如Bi，In或Zn的熔点降低元素，以及用于改善抗冲击性的元素如Sb。

公开(公告)号：US20100025837A1

公开(公告)日：2010-02-04

申请号：US12446827

申请日：2007-10-22

申请人： Tomonori Shinoda ,  Hironori Shizuhata ,  Hirofumi Shinoda ,  Yuji Kawamata ,  Takeshi Tashima ,  Masato Shimamura ,  Masako Watanabe ,  Masazumi Amagai

发明人： Tomonori Shinoda ,  Hironori Shizuhata ,  Hirofumi Shinoda ,  Yuji Kawamata ,  Takeshi Tashima ,  Masato Shimamura ,  Masako Watanabe ,  Masazumi Amagai

IPC分类号： H01L25/065 ,  H01L23/522 ,  H01L21/70

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： The present invention relates to a complex type semiconductor device formed by laminating plural semiconductor packages, wherein it comprises: an upper semiconductor package which comprises a substrate for wiring and connecting provided with electrodes for conducting packages on a lower surface in the upper semiconductor package and a principal part of the upper semiconductor package disposed on an upper surface and/or a lower surface of the above substrate and which constitutes a relatively upper part, a lower semiconductor package which comprises a substrate for wiring and connecting provided with electrodes for conducting packages on an upper surface in the lower semiconductor package and a principal part of the lower semiconductor package disposed on an upper surface and/or a lower surface of the above substrate and which constitutes a relatively lower part, a spacer sheet which comprises a space part corresponding to the principal part of the upper semiconductor package and/or the principal part of the lower semiconductor package disposed between the adjacent upper and lower substrates and through holes disposed in a periphery of the above space part and allowing the electrodes oppositely disposed between the substrates to be communicated with each other and which is adhered onto the above substrates and inserted therebetween, connection terminals which are provided in an inside of the through holes in the spacer sheet and which are used for conducting the substrates and connection terminals for external connection which are formed on a lower surface of a substrate for wiring and connecting in a semiconductor package located in a lowermost part and to a production process for the same. The present invention provides a wiring and connecting method by a spacer sheet which ensures an installation space between an upper semiconductor package and a lower semiconductor package in a POP type semiconductor package and prevents short circuit between adjacent connection terminals and which can certainly wire and connect both semiconductor packages, and a complex type semiconductor device of a POP type having a high packaging density prepared is provided by the above method.

公开(公告)号：US20100090323A1

公开(公告)日：2010-04-15

申请号：US12446813

申请日：2007-10-22

申请人： Tomonori Shinoda ,  Hironori Shizuhata ,  Hirofumi Shinoda ,  Yuji Kawamata ,  Takeshi Tashima ,  Masato Shimamura ,  Masako Watanabe ,  Masazumi Amagai

发明人： Tomonori Shinoda ,  Hironori Shizuhata ,  Hirofumi Shinoda ,  Yuji Kawamata ,  Takeshi Tashima ,  Masato Shimamura ,  Masako Watanabe ,  Masazumi Amagai

IPC分类号： H01L23/52 ,  H05K7/00 ,  H01L21/60

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： The present invention provides a spacer sheet for a complex type semiconductor device provided between the semiconductor packages of a complex type semiconductor device formed by laminating plural semiconductor packages, comprising through holes of an array corresponding to electrodes which can be provided onto a substrate of one semiconductor package and which are formed in order to connect and wire one semiconductor package with the other semiconductor package and a space part corresponding to a principal part of the above one semiconductor package mounted on the substrate or a principal part of the other semiconductor package opposed to the substrate and a production process for a complex type semiconductor device in which the above spacer sheet is used. It further provides a wiring and connecting method by using a spacer sheet which satisfies securing of a distance between connection terminals and a narrow pitch at the same time in a POP type semiconductor package and a complex type semiconductor device of a POP type which is increased in a packaging density by the above wiring and connecting method.

摘要翻译： 本发明提供了一种复合型半导体器件的间隔片，其设置在通过层叠多个半导体封装形成的复合型半导体器件的半导体封装之间，该半导体封装包括与可设置在一个半导体的衬底上的电极相对应的阵列的通孔 封装，并且其形成以便将一个半导体封装与另一个半导体封装连接并布线，并且与安装在基板上的上述一个半导体封装的主要部分相对应的空间部分或与其相对的另一个半导体封装的主要部分 基板和其中使用上述间隔片的复合型半导体器件的制造方法。 它还通过使用在POP型半导体封装中同时满足连接端子之间的距离和窄间距的间隔片以及POP型的复合型半导体器件进一步提供布线和连接方法，所述复合型半导体器件增加 通过上述布线和连接方法的封装密度。

公开(公告)号：US07861953B2

公开(公告)日：2011-01-04

申请号：US11855336

申请日：2007-09-14

申请人： Kazuyuki Naka ,  Takeshi Tashima

发明人： Kazuyuki Naka ,  Takeshi Tashima

IPC分类号： B05B1/00 ,  C04B35/00

CPC分类号： B01F5/0682 ,  B01F3/12 ,  B01F5/0689 ,  B28C5/06 ,  C04B35/4682 ,  C04B35/62635 ,  C04B35/6264 ,  C04B2235/5445 ,  C04B2235/77 ,  C04B2235/963 ,  H01C7/18 ,  H01G4/12 ,  H01G4/30 ,  H01G13/00 ,  Y02P40/63

摘要： A dispersing apparatus that can efficiently disperse agglomerated particles in a slurry at a lower energy, a method for preparing a ceramic slurry containing ceramic particles that have been dispersed with the dispersing apparatus, a reliable monolithic ceramic electronic component manufactured using ceramic green sheets formed of the ceramic slurry, and a method for manufacturing the monolithic ceramic electronic component. A slurry containing agglomerated particles is passed through a dispersing section to produce a tensile stress, and the tensile stress is applied to the agglomerated particles in the slurry, thereby dispersing the agglomerated particles. The dispersing section includes a nozzle, a first channel thorough which a jet generated through the nozzle passes, and a cylindrical second channel through which the jet coming through the first channel passes to produce a tensile stress. The nozzle, the first channel, and the second channel are disposed in that order from the upstream side to the downstream side.

摘要翻译： 能够以较低的能量高效地分散在浆料中的分散装置的分散装置，制备含有分散装置分散的陶瓷粒子的陶瓷浆料的方法，使用由陶瓷生片形成的陶瓷生片制造的可靠的单片陶瓷电子部件 陶瓷浆料及其制造方法。 含有附聚颗粒的浆料通过分散部分产生拉伸应力，并且将拉伸应力施加到浆料中的附聚颗粒，从而分散附聚颗粒。 分散部分包括喷嘴，通过喷嘴产生的喷嘴通过的第一通道和通过第一通道的射流通过的圆柱形第二通道通过以产生拉伸应力。 喷嘴，第一通道和第二通道以从上游侧到下游侧的顺序设置。

公开(公告)号：US08310805B2

公开(公告)日：2012-11-13

申请号：US12481694

申请日：2009-06-10

申请人： Takeshi Tashima ,  Hiroyuki Matsumoto

发明人： Takeshi Tashima ,  Hiroyuki Matsumoto

IPC分类号： H01G4/005 ,  H01G4/06

CPC分类号： H01G4/232 ,  H01G4/012 ,  H01G4/2325 ,  H01G4/30 ,  Y10T29/435

摘要： A multilayer ceramic electronic component includes external terminal electrodes that are formed by direct plating on the first and second side surfaces of a ceramic body including stacked ceramic layers and inner conductors. The external terminal electrodes include base plating films formed so as to cover the exposed portions of inner conductors. Voids are provided that are open to the side surfaces of the ceramic body so as to be adjacent to the ends in the width direction of the exposed portions of the inner conductors. A plating metal defining the base plating films enters the voids and is electrically connected to the inner conductors in the ceramic body.

摘要翻译： 多层陶瓷电子部件包括通过在陶瓷体的第一和第二侧面上直接电镀形成的外部端子电极，该陶瓷体包括层叠的陶瓷层和内部导体。 外部端子电极包括形成为覆盖内部导体的暴露部分的基底镀膜。 设有向陶瓷体的侧面开放的空隙，以与内导体的露出部的宽度方向的端部相邻。 限定基底镀膜的电镀金属进入空隙并与陶瓷体中的内部导体电连接。