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公开(公告)号：US20040177313A1
公开(公告)日：2004-09-09
申请号：US10748242
申请日：2003-12-31
IPC分类号： H03M013/03
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions, a decoding unit that decodes the instructions fetched by the instruction fetching unit; and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register-register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data. The first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs new path metrics.
摘要翻译： 提供能够执行维特比算法的数字信号处理器。 数字信号处理器包括取指令的指令取出单元，对由指令取出单元取出的指令进行解码的解码单元; 以及执行单元，执行由解码单元解码的指令。 执行单元包括被配置为执行寄存器寄存器算术逻辑运算的算术逻辑单元。 算术逻辑单元与第三数据与第四数据的比较并行地将第一数据与第二数据进行比较。 第一数据，第二数据，第三数据和第四数据可以分别是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。 执行单元输出新的路径度量。
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公开(公告)号：US20020016946A1
公开(公告)日：2002-02-07
申请号：US09974807
申请日：2001-10-12
IPC分类号： H03M013/03
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1nullBM1 to the value of PM0nullBM0. A path metric of a new state Nnull2knull2 is formed by comparing the value of PM1nullBM0 to PM0nullBM1.
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公开(公告)号：US20030066022A1
公开(公告)日：2003-04-03
申请号：US10252394
申请日：2002-09-24
IPC分类号： H03M013/03
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.
摘要翻译： 提供能够执行维特比算法的数字信号处理器。 数字信号处理器包括取指令的指令取出单元; 对由指令取出单元取出的指令进行解码的解码单元，以及执行由解码单元解码的指令的执行单元。 执行单元包括将第一数据与第二数据进行比较的第一比较单元和将第三数据与第四数据进行比较的第二比较单元。 第一比较单元和第二比较单元并行操作。 此外，第一数据，第二数据，第三数据和第四数据可以分别是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。 执行单元分别在高阶位置和低位置输出任何两个新的路径度量。
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