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公开(公告)号：US08536675B2
公开(公告)日：2013-09-17
申请号：US13364153
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
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公开(公告)号：US08338225B2
公开(公告)日：2012-12-25
申请号：US13350817
申请日：2012-01-16
IPC分类号： H01L21/06
CPC分类号： H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1683
摘要： A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.
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公开(公告)号：US20120280197A1
公开(公告)日：2012-11-08
申请号：US13550091
申请日：2012-07-16
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译： 一种具有平底下电极的相变存储单元及其制造方法。 该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面 导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极 。
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4.发明授权公开(公告)号：US08138056B2
公开(公告)日：2012-03-20
申请号：US12497596
申请日：2009-07-03
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
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公开(公告)号：US08101456B2
公开(公告)日：2012-01-24
申请号：US12243759
申请日：2008-10-01
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1683
摘要： A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.
摘要翻译： 存储单元结构和形成这种结构的方法。 该方法部分地包括在底部电极的中心上形成氧化层内的通孔。 该方法包括沿通孔的侧壁沉积通孔间隔物并氧化通孔间隔物。 通孔间隔件由具有至少一个半的起珠床比的材料组成，并且当被氧化时是绝缘体。 在氧化期间通孔间隔物的膨胀减小了通孔面积。 或者，该方法部分地包括在底部电极的中心之上在第一层内形成通孔。 第一层具有至少一个半的Pilling-Bedworth比，并且当被氧化时是绝缘体。 该方法还包括在第一层中氧化通孔的侧壁的至少一部分。
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6.发明申请公开(公告)号：US20110275209A1
公开(公告)日：2011-11-10
申请号：US13185055
申请日：2011-07-18
IPC分类号： H01L21/28
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译： 垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。 半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。 或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。 用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。
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7.发明授权Method for fabricating a vertical field effect transistor array comprising a plurality of semiconductor pillars 有权一种制造包括多个半导体柱的垂直场效应晶体管阵列的方法公开(公告)号：US07981748B2
公开(公告)日：2011-07-19
申请号：US12541495
申请日：2009-08-14
IPC分类号： H01L21/308
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译： 垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。 半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。 或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。 用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。
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公开(公告)号：US07682945B2
公开(公告)日：2010-03-23
申请号：US12025333
申请日：2008-02-04
IPC分类号： H01L21/20
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1683 , Y10S438/90
摘要： The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.
摘要翻译： 本发明在一个实施例中提供了形成存储器件的方法，该存储器件包括提供包括具有第一宽度的导电柱的层间电介质层; 形成包括金属层和第一绝缘层的堆叠; 在层叠电介质层的与堆叠的每个侧壁相邻的部分上方形成第二绝缘层; 去除所述第一绝缘层以提供空腔; 在所述第二绝缘层和所述空腔的顶部形成保形绝缘层; 向保形绝缘层施加各向异性蚀刻步骤以产生具有暴露金属层的上表面的第二宽度的开口，其中第一宽度大于第二宽度; 并在开口中形成记忆材料层。
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公开(公告)号：US20090194757A1
公开(公告)日：2009-08-06
申请号：US12025333
申请日：2008-02-04
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1683 , Y10S438/90
摘要： The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.
摘要翻译： 本发明在一个实施例中提供了形成存储器件的方法，该存储器件包括提供包括具有第一宽度的导电柱的层间电介质层; 形成包括金属层和第一绝缘层的堆叠; 在层叠电介质层的与堆叠的每个侧壁相邻的部分上方形成第二绝缘层; 去除所述第一绝缘层以提供空腔; 在所述第二绝缘层和所述空腔的顶部形成保形绝缘层; 向保形绝缘层施加各向异性蚀刻步骤以产生具有暴露金属层的上表面的第二宽度的开口，其中第一宽度大于第二宽度; 并在开口中形成记忆材料层。
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公开(公告)号：US20090189139A1
公开(公告)日：2009-07-30
申请号：US12021577
申请日：2008-01-29
IPC分类号： H01L45/00
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.
摘要翻译： 提供一种制造电极的方法，其包括在电介质层的导电结构的顶部设置第一相变材料的柱; 或倒置结构; 在电介质层的上方形成绝缘材料，并邻近所述柱，其中所述第一绝缘材料的上表面与所述柱的上表面共面; 将所述柱的上表面凹陷在所述绝缘材料的上表面下方以提供凹腔; 以及在所述凹腔和所述绝缘材料的上表面之上形成第二相变材料，其中所述第二相变材料具有比所述第一相变材料更大的相电阻率。
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