公开(公告)号：US09726696B2

公开(公告)日：2017-08-08

申请号：US13723417

申请日：2012-12-21

Applicant: Matthew Powell ,  David R. Welland

Inventor： Matthew Powell ,  David R. Welland

IPC: G01K7/00 ,  G01R19/00 ,  G05F3/02 ,  G01R35/00 ,  G01K7/01

CPC classification number: G01R19/0069 ,  G01K7/01 ,  G01R35/00 ,  G05F3/02

Abstract: In one form, a reference circuit includes a measurement circuit and a determination circuit. The measurement circuit has an output for providing a ratio of a difference in base-to-emitter voltage (VBE) of a bipolar device at different current densities to a VBE of the bipolar device at a first current density. The determination circuit has an input coupled to the measurement circuit, and an output for providing a digital value of a parameter in response to the ratio. In another form, the reference circuit further includes a voltage generation circuit having an input coupled to the determination circuit, and an output, for modulating an analog voltage using the digital value to provide a reference voltage to the output, wherein the reference voltage is temperature compensated over a temperature range.

公开(公告)号：US20140084899A1

公开(公告)日：2014-03-27

申请号：US13723417

申请日：2012-12-21

Applicant: Matthew Powell ,  David R. Welland

Inventor： Matthew Powell ,  David R. Welland

IPC: G01R19/00 ,  G01R35/00 ,  G05F3/02

CPC classification number: G01R19/0069 ,  G01K7/01 ,  G01R35/00 ,  G05F3/02

Abstract: In one form, a reference circuit includes a measurement circuit and a determination circuit. The measurement circuit has an output for providing a ratio of a difference in base-to-emitter voltage (VBE) of a bipolar device at different current densities to a VBE of the bipolar device at a first current density. The determination circuit has an input coupled to the measurement circuit, and an output for providing a digital value of a parameter in response to the ratio. In another form, the reference circuit further includes a voltage generation circuit having an input coupled to the determination circuit, and an output, for modulating an analog voltage using the digital value to provide a reference voltage to the output, wherein the reference voltage is temperature compensated over a temperature range.

Abstract translation: 在一种形式中，参考电路包括测量电路和确定电路。 测量电路具有输出，用于以不同的电流密度提供双极型器件的基极 - 发射极间电压（VBE）与第一电流密度的双极器件的VBE的比值。 确定电路具有耦合到测量电路的输入端和用于响应该比率提供参数的数字值的输出端。 在另一种形式中，参考电路还包括具有耦合到确定电路的输入的电压产生电路和用于使用数字值调制模拟电压以向输出提供参考电压的输出，其中参考电压为温度 在温度范围内进行补偿。

公开(公告)号：US09095041B2

公开(公告)日：2015-07-28

申请号：US11930804

申请日：2007-10-31

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03K5/00 ,  H05K9/00 ,  H03L7/18 ,  H05K1/02 ,  H05K3/10

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

公开(公告)号：US20120169659A1

公开(公告)日：2012-07-05

申请号：US13335407

申请日：2011-12-22

Applicant: David R. Welland

Inventor： David R. Welland

IPC: G06F3/045

CPC classification number: G06F3/044 ,  G06F3/0416

Abstract: A method for interfacing with a capacitive touch screen is disclosed. The method includes charging an internal capacitor in the touch screen, which internal capacitor is disposed proximate a fixed location on the touch screen and is capable of changing in response to a touch at that location on the touch screen. After charging, value of the charge on the internal capacitor is determined in a manner to reduce effects of interference.

Abstract translation: 公开了一种用于与电容式触摸屏接口的方法。 该方法包括对触摸屏中的内部电容器进行充电，该内部电容器设置在触摸屏上的固定位置附近，并且能够响应于触摸屏上该位置处的触摸而改变。 充电后，以减少干扰影响的方式确定内部电容器的电荷值。

公开(公告)号：US08154336B2

公开(公告)日：2012-04-10

申请号：US11930596

申请日：2007-10-31

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03K5/00

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract translation: 提供一种减少电路干扰的方法和装置。 提供管理策略，以减少参考杂散和电路干扰。 管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。 这些技术可以单独使用，或者优选地彼此组合使用。

公开(公告)号：US20100102876A1

公开(公告)日：2010-04-29

申请号：US12650545

申请日：2009-12-31

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03B1/04

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

公开(公告)号：US07522193B2

公开(公告)日：2009-04-21

申请号：US10862488

申请日：2004-06-07

Applicant: Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

Inventor： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

IPC: H04N5/235 ,  H04N5/228 ,  H04N5/217

CPC classification number: H04N5/2352

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

Abstract translation: 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括基于直方图的自动增益控制（AGC）电路，其首先通过调整所述CCD系统来控制增益，然后对于较高的增益电平进行增益，使所述 CDSVGA电路和数字增益电路，以产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

公开(公告)号：US07515672B2

公开(公告)日：2009-04-07

申请号：US10679013

申请日：2003-10-03

Applicant: Timothy J. Dupuis ,  George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

Inventor： Timothy J. Dupuis ,  George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC: H04L23/00

CPC classification number: H04L25/06 ,  H04L7/033 ,  H04L25/0266 ,  H04M11/06 ,  H04M19/001

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable circuit for the DC termination for a variety of international phone standards. The invention may also be utilized with circuitry for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

Abstract translation: 可以使用数字直接访问布置（DAA）电路来终止在用户端的电话连接，其提供用于到达和来自电话线的信号的通信路径。 简要描述，DAA为各种国际电话标准的DC终端提供可编程电路。 本发明还可以用于跨电容隔离屏障发送和接收信号的电路。 更具体地，提供了一种DC可编程直流限流模式可用的直流保持电路。 在限流模式下，功率可能会在DAA集成电路外部的器件中耗散。 此外，大部分功率可能会在外部无源器件（如电阻）中消散。

公开(公告)号：US07362841B2

公开(公告)日：2008-04-22

申请号：US10292290

申请日：2002-11-12

Applicant: Timothy J. Dupuis ,  George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

Inventor： Timothy J. Dupuis ,  George Tyson Tuttle ,  Jeffrey W. Scott ,  Navdeep S. Sooch ,  David R. Welland

IPC: H04L23/00

CPC classification number: H04L25/06 ,  H04L7/033 ,  H04L25/0266 ,  H04M11/06 ,  H04M19/001

Abstract: A digital direct access arrangement (DAA) circuitry may be used to terminate the telephone connections at the user's end that provides a communication path for signals to and from the phone lines. Briefly described, the DAA provides a programmable means for the DC termination for a variety of international phone standards. The invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier. More particularly, a DC holding circuit is provided in which a programmable DC current limiting mode is available. In the current limiting mode, power may be dissipated in devices external to a DAA integrated circuit. Moreover, much of the power may be dissipated in external passive devices, such as resistors.

Abstract translation: 可以使用数字直接访问布置（DAA）电路来终止在用户端的电话连接，其提供用于到达和来自电话线的信号的通信路径。 简要描述，DAA提供用于各种国际电话标准的DC终端的可编程装置。 本发明还可以用于在电容隔离屏障上传输和接收信号的装置。 更具体地，提供了一种DC可编程直流限流模式可用的直流保持电路。 在限流模式下，功率可能会在DAA集成电路外部的器件中耗散。 此外，大部分功率可能会在外部无源器件（如电阻）中消散。

公开(公告)号：US07289145B2

公开(公告)日：2007-10-30

申请号：US11415000

申请日：2006-05-01

Applicant: Sandra Marie Johnson ,  Shih-Chung Chao ,  Nadi Rafik Itani ,  Caiyi Wang ,  Brannon Craig Harris ,  Ash Prabala ,  Douglas R. Holberg ,  Alan Hansford ,  Syed Khalid Azim ,  David R. Welland

Inventor： Sandra Marie Johnson ,  Shih-Chung Chao ,  Nadi Rafik Itani ,  Caiyi Wang ,  Brannon Craig Harris ,  Ash Prabala ,  Douglas R. Holberg ,  Alan Hansford ,  Syed Khalid Azim ,  David R. Welland

IPC: H04N5/235

CPC classification number: H04N5/3575 ,  H04N5/335 ,  H04N5/361

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

Abstract translation: 用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括用于从CCD系统接收数据的相关双样本和可变增益（CDSVGA）电路以及首先通过调整来控制增益的自动增益控制（AGC）电路 所述CCD系统然后为了更高的增益水平，使得所述CDSVGA电路和数字增益电路中的增益调整产生组合的目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路。 处理电路包括模拟前端和数字信号处理系统，用于捕获全运动视频并输出CCIR 601 4：2：2 YCrCb视频数据输出以便呈现在用户选择的显示器上。