摘要:
A method for correcting the phase of a clock in a data receiver which receives a data flow representing different signal levels with logical high and low signal values and signal transitions positioned therebetween, wherein the positions of such signal transitions between respective two adjacent logical signal values are evaluated for correcting the phase of the clock. The position of a signal transition between a first pair of signal values on one level (11) or a second pair of signal values on the other level (00) is weighted stronger in the evaluation then the positions of signal transitions between adjacent single signal values (1,0) of different signal levels.
摘要:
A method of adjusting equalization parameters in a receiver wherein a bit error rate (BER) in a data stream is measured from the number of corrected bits in data blocks which have an information section and an error correction section. A predetermined equalization parameter is changed, and the bit error rate (BER) after change is again measured to find out how to change the predetermined equalization parameter until an optimum is reached.When adjusting the threshold value of the receiver, the history of occurring bits preceding the actual sampled bit is taken into consideration in that the amount and direction of adjustment is derived from a look-up table.