公开(公告)号：US08350339B2

公开(公告)日：2013-01-08

申请号：US12795144

申请日：2010-06-07

Applicant: Mei-Hui Huang ,  Chan-Hong Chern

Inventor： Mei-Hui Huang ,  Chan-Hong Chern

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L27/088 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/0207 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/66545

Abstract: An integrated circuit includes at least one first gate electrode of at least one active transistor. At least one first dummy gate electrode is disposed adjacent to a first side edge of the at least one first gate electrode. At least one second dummy gate electrode is disposed adjacent to a second side edge of the at least one first gate electrode. The second side edge is opposite to the first side edge. At least one guard ring is disposed around the at least one first gate electrode, the at least one first dummy gate electrode, and the at least one second dummy gate electrode. An ion implantation layer of the at least one guard ring substantially touches at least one of the at least one first dummy gate electrode and the at least one second dummy gate electrode.

Abstract translation: 集成电路包括至少一个有源晶体管的第一栅电极。 至少一个第一虚拟栅电极设置成与所述至少一个第一栅电极的第一侧边缘相邻。 至少一个第二伪栅电极设置成与所述至少一个第一栅电极的第二侧边相邻。 第二侧边缘与第一侧边缘相对。 至少一个保护环布置在所述至少一个第一栅电极，所述至少一个第一虚拟栅极电极和所述至少一个第二虚拟栅电极周围。 所述至少一个保护环的离子注入层基本上接触所述至少一个第一伪栅极电极和所述至少一个第二虚设栅极电极中的至少一个。

公开(公告)号：US09524934B2

公开(公告)日：2016-12-20

申请号：US13302335

申请日：2011-11-22

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Kuoyuan (Peter) Hsu

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Kuoyuan (Peter) Hsu

IPC: H01L21/8238 ,  H01L23/525 ,  H01L27/06 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L23/5256 ,  H01L21/823437 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.

Abstract translation: 形成集成电路的方法包括在衬底上形成至少一个晶体管。 形成至少一个晶体管包括在衬底上形成栅极电介质结构。 在栅介电结构上形成功函数金属层。 在功函数金属层上形成导电层。 源极/漏极（S / D）区域形成为与栅极电介质结构的每个侧壁相邻。 在衬底上形成至少一个电熔丝。 形成至少一个电熔丝包括在衬底上形成第一半导体层。 在第一半导体层上形成第一硅化物层。

公开(公告)号：US08884665B2

公开(公告)日：2014-11-11

申请号：US13084817

申请日：2011-04-12

Applicant: Chih-Chang Lin ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung

Inventor： Chih-Chang Lin ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung

IPC: H03B19/00 ,  H03K5/15

CPC classification number: H03K5/15013

Abstract: A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.

Abstract translation: 多相时钟发生器包括至少一个分频器级。 时钟信号作为第一级时钟输入提供给分频器的第一级中的分频器。 第N级包括2N个分频器，其中N是正整数。 第一级中的每个分频器被配置为将第一级时钟输入的第一时钟频率除以2以提供第一级输出。 第N级中的每个除法器被配置为将输入的第N级时钟的第N个时钟频率除以2以提供第N级输出。 在第N级的分频器的第N级输出提供2N相位时钟信号，它们在相邻的相位时钟信号之间以相同的相位差均匀分布。

公开(公告)号：US08872592B2

公开(公告)日：2014-10-28

申请号：US13527365

申请日：2012-06-19

Applicant: Tsung-Ching Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin

Inventor： Tsung-Ching Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin

IPC: H03F3/08

CPC classification number: H03F3/082 ,  H03F1/0205 ,  H03F3/08 ,  H03F3/3022 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/216 ,  H03F2203/30031 ,  H03F2203/45222 ,  H03F2203/45644 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03F2203/45724

Abstract: A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.

Abstract translation: 跨阻放大器包括具有第一输入节点和第一输出节点的第一反相器。 第一输入节点被配置为耦合到输入信号。 第二反相器具有第二输入节点和第二输出节点。 第二输入节点被配置为接收参考电压端子。 第一反相器和第二反相器被配置为在第一输出节点和第二输出节点之间提供差分输出电压信号。

公开(公告)号：US08862951B2

公开(公告)日：2014-10-14

申请号：US13528877

申请日：2012-06-21

Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

IPC: G06F11/00 ,  H04L27/01

CPC classification number: H04L25/03057 ,  H04L25/06 ,  H04L25/08

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract translation: 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。

公开(公告)号：US08661389B2

公开(公告)日：2014-02-25

申请号：US13084748

申请日：2011-04-12

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Li-Chun Tien

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Li-Chun Tien

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of designing an integrated circuit includes providing a cell library including a first and second cell structures. The cell structures each include a dummy gate electrode disposed on a boundary. An edge gate electrode is disposed adjacent to the dummy gate electrode. An oxide definition (OD) region has an edge disposed between the edge gate electrode and the dummy gate electrode. The method includes determining if the cell structures are to be abutted with each other. If so, the method includes abutting the cell structures. If not so, the method includes increasing areas of portions of the OD regions between the edge gate electrodes and the dummy gate electrodes.

Abstract translation: 设计集成电路的方法包括提供包括第一和第二单元结构的单元库。 电池结构各自包括设置在边界上的虚拟栅电极。 边缘栅电极被设置成与虚拟栅电极相邻。 氧化物定义（OD）区域具有设置在边缘栅电极和伪栅电极之间的边缘。 该方法包括确定单元结构是否彼此邻接。 如果是，则该方法包括邻接单元结构。 如果不是这样，则该方法包括增加边缘栅极电极和虚拟栅电极之间的OD区域的部分区域。

公开(公告)号：US08378756B2

公开(公告)日：2013-02-19

申请号：US12782064

申请日：2010-05-18

Applicant: Ming-Chieh Huang ,  Chiang Pu ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Ming-Chieh Huang ,  Chiang Pu ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H03B5/30 ,  G01C19/00

CPC classification number: H03B5/30

Abstract: Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.

Abstract translation: 一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

公开(公告)号：US08354862B2

公开(公告)日：2013-01-15

申请号：US13448878

申请日：2012-04-17

Applicant: Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

Inventor： Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

IPC: H03D13/00

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.

Abstract translation: 包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于 输入信号。 电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是 晚于输入信号。 电路还包括被配置为产生第一增加信号的第三电路。 电路还包括被配置为产生第一减小信号的第四电路。

公开(公告)号：US08321828B2

公开(公告)日：2012-11-27

申请号：US12684819

申请日：2010-01-08

Applicant: Chan-Hong Chern

Inventor： Chan-Hong Chern

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0692

Abstract: A method of forming an integrated circuit structure on a chip includes extracting an active layer from a design of the integrated circuit structure, forming a guard band conforming to the shape of the active layer, the guard band surrounds the active layer, and the guard band is spaced from the active layer at a first spacing in the X-axis direction and at a second spacing in the Y-axis direction, removing any part of the guard band that violates design rules, removing convex corners of the guard band, and adding dummy diffusion patterns into the remaining space of the chip outside the guard band. The first and second spacing can be specified as the same spacings in a Spice model characterization of the integrated circuit structure. The dummy diffusion patterns with different granularities can be added so that the diffusion density is substantially uniform over the chip.

Abstract translation: 在芯片上形成集成电路结构的方法包括从集成电路结构的设计中提取有源层，形成符合有源层形状的保护带，保护带围绕有源层，保护带 与有源层以X轴方向的第一间隔和Y轴方向上的第二间隔与有源层间隔开，去除违反设计规则的保护带的任何部分，去除保护带的凸角，并添加 伪散射图案进入保护带外部芯片的剩余空间。 在集成电路结构的Spice模型表征中，第一和第二间隔可以被指定为相同的间距。 可以添加具有不同粒度的虚拟扩散图案，使得扩散密度在芯片上基本均匀。

公开(公告)号：US08179162B2

公开(公告)日：2012-05-15

申请号：US12835130

申请日：2010-07-13

Applicant: Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

Inventor： Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

IPC: H03D13/00 ,  H03L7/06

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

Abstract translation: 一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。