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公开(公告)号：US11621920B2
公开(公告)日：2023-04-04
申请号：US17902834
申请日：2022-09-04
发明人： Avi Urman , Lior Narkis , Omri Kahalon
IPC分类号： H04L47/20 , H04L47/2466 , H04L47/2475 , G06F9/455 , H04L47/783 , H04L47/12
摘要： A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.
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公开(公告)号：US11190462B2
公开(公告)日：2021-11-30
申请号：US16693302
申请日：2019-11-24
发明人： Dotan David Levi , Avi Urman , Lior Narkis
IPC分类号： G06F15/16 , H04L12/939 , H04L12/861 , H04W28/04 , H04L29/06 , H04L12/879
摘要： Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.
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公开(公告)号：US20210344600A1
公开(公告)日：2021-11-04
申请号：US16865567
申请日：2020-05-04
发明人： Avi Urman , Lior Narkis , Noam Bloch , Eyal Srebro , Shay Aisman
IPC分类号： H04L12/801 , H04L12/835 , H04L12/823
摘要： A network adapter includes a host interface, a network interface, a memory and packet processing circuitry. The memory holds a shared buffer and multiple queues allocated to the multiple host processors. The packet processing circuitry is configured to receive from the network interface data packets destined to the host processors, to store payloads of at least some of the data packets in the shared buffer, to distribute headers of at least some of the data packets to the queues, to serve the data packets to the host processors by applying scheduling among the queues, to detect congestion in the data packets destined to a given host processor among the host processors, and, in response to the detected congestion, to mitigate the congestion in the data packets destined to the given host processor, while retaining uninterrupted processing of the data packets destined to the other host processors.
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公开(公告)号：US10382350B2
公开(公告)日：2019-08-13
申请号：US15701459
申请日：2017-09-12
发明人： Dror Bohrer , Noam Bloch , Lior Narkis , Hillel Chapman , Gilad Hammer
IPC分类号： G06F9/455 , H04L12/741 , H04L12/813 , H04L12/863 , H04L12/931
摘要： Network interface apparatus includes a host interface and a network interface, which receives packets in multiple packet flows destined for one or more virtual machines running on a host processor. Packet processing circuitry receives a first instruction from the host processor to offload preprocessing of the data packets in a specified flow in accordance with a specified rule, and initiates preprocessing of the data packets while writing one or more initial data packets from the specified flow to a temporary buffer. Upon subsequently receiving a second instruction to enable the specified rule, the initial data packets are delivered from the temporary buffer, after preprocessing by the packet processing circuitry, directly to a virtual machine to which the specified flow is destined, followed by preprocessing and delivery of subsequent data packets in the specified flow to the virtual machine.
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公开(公告)号：US09462047B2
公开(公告)日：2016-10-04
申请号：US14637414
申请日：2015-03-04
发明人： Noam Bloch , Eitan Hirshberg , Michael Kagan , Lior Narkis
IPC分类号： H04L12/28 , H04L29/08 , H04L12/715 , H04L12/46 , G06F9/455
CPC分类号： H04L67/10 , G06F9/45533 , H04L12/4633 , H04L45/64
摘要： A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.
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公开(公告)号：US20150271244A1
公开(公告)日：2015-09-24
申请号：US14658260
申请日：2015-03-16
发明人： Noam Bloch , Ariel Shachar , Michael Kagan , Lior Narkis , Shlomo Raikin
CPC分类号： H04L67/02 , G06F9/45558 , G06F2009/45595 , H04L67/2842 , H04L69/40
摘要： A network interface device includes a host interface for connection to a host processor and a network interface, which is configured to transmit and receive data packets over a network, and which comprises multiple distinct physical ports configured for connection to the network. Processing circuitry is configured to receive, via one of the physical ports, a data packet from the network and to decide, responsively to a destination identifier in the packet, whether to deliver a payload of the data packet to the host processor via the host interface or to forward the data packet to the network via another one of the physical ports.
摘要翻译： 网络接口设备包括用于连接到主处理器的主机接口和网络接口，网络接口被配置为通过网络发送和接收数据分组，并且包括被配置为连接到网络的多个不同的物理端口。 处理电路被配置为经由物理端口中的一个接收来自网络的数据分组，并且响应于分组中的目的地标识符来决定是否经由主机接口将数据分组的有效载荷传送到主机处理器 或者通过另一个物理端口将数据分组转发到网络。
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公开(公告)号：US20220417157A1
公开(公告)日：2022-12-29
申请号：US17902834
申请日：2022-09-04
发明人： Avi Urman , Lior Narkis , Omri Kahalon
IPC分类号： H04L47/20 , H04L47/2466 , G06F9/455 , H04L47/12 , H04L47/2475 , H04L47/783
摘要： A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.
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公开(公告)号：US20220231953A1
公开(公告)日：2022-07-21
申请号：US17151705
申请日：2021-01-19
发明人： Avi Urman , Lior Narkis , Omri Kahalon
IPC分类号： H04L12/813 , H04L12/855 , H04L12/859 , H04L12/801 , G06F9/455 , H04L12/911
摘要： A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.
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公开(公告)号：US20220217101A1
公开(公告)日：2022-07-07
申请号：US17142366
申请日：2021-01-06
发明人： Gal Yefet , Daniel Marcovitch , Roee Moyal , Ariel Shahar , Gil Bloch , Lior Narkis
IPC分类号： H04L12/879 , H04L12/861 , H04L12/937 , H04L12/24
摘要： A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry.
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公开(公告)号：US11277455B2
公开(公告)日：2022-03-15
申请号：US16430457
申请日：2019-06-04
发明人： Dotan David Levi , Alex Vainman , Natan Manevich , Nir Nitzani , Ilan Smith , Richard Hastie , Noam Bloch , Lior Narkis , Rafi Weiner
IPC分类号： H04L29/06 , H04L12/861 , H04L12/851 , H04L12/841 , H04L12/801 , H04L12/823 , H04L65/613 , H04L65/80 , H04L67/01 , H04L49/90 , H04L47/2441 , H04L47/28 , H04L47/34 , H04L47/32 , H04L29/08 , H04L67/06
摘要： A method including configuring a transmit process to store information including a queue of packets to be transmitted, the queue defining transmit process packets to be transmitted, each packet associated with a transmission time, and configuring a synchronization process to receive from the transmit process at least some of the information. The synchronization process performs one of: A) accessing a dummy send queue and a completion queue, and transmitting one or more of the transmit process packets in accordance with a completion queue entry in the completion queue, and B) sends a doorbell to transmission hardware at a time when at least one of the transmit process packets is to be transmitted, the synchronization process including a master queue configured to store transmission entries, each transmission entry including a transmit process indicator and an indication of transmit process packets to be transmitted. Related apparatus and methods are also described.
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