公开(公告)号：US20050266652A1

公开(公告)日：2005-12-01

申请号：US10709768

申请日：2004-05-27

申请人： Michael Chudzik ,  Louis Hsu ,  Joseph Shepard ,  William Tonti

发明人： Michael Chudzik ,  Louis Hsu ,  Joseph Shepard ,  William Tonti

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L23/522

CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L23/5227 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.

摘要翻译： 用于利用垂直交错电极的结构，装置和方法用于增加电容器面积，同时保持最小的水平脚印。 由于电容与表面积成比例，因此该结构能够连续使用当前厚度的当前介电材料，例如Si 3 N 4。 在叉指MIMCAP结构的第二实施例中，电极以螺旋方式形成，其用于增加MIMCAP的物理强度。 还包括螺旋形电容器电极，其通过提供电路设计者容易指定的宽范围的离散电容值来适应模块化设计。

公开(公告)号：US20070128859A1

公开(公告)日：2007-06-07

申请号：US11164684

申请日：2005-12-01

申请人： Michael Chudzik ,  Joseph Shepard

发明人： Michael Chudzik ,  Joseph Shepard

IPC分类号： H01L21/4763 ,  H01L21/44 ,  C23C16/00

CPC分类号： G03F7/168 ,  G03F7/0035

摘要： A stepper is combined with hardware that deposits a layer of material in the course of forming an integrated circuit, thus performing the deposition, patterning and cleaning without exposing the wafer to a transfer between tools and combining the function of three tools in a composite tool. The pattern-defining material is removed by the application of UV light through the mask of the stepper, thereby eliminating the bake and development steps of the prior art method. Similarly, a flood exposure of UV eliminates the cleaning steps of the prior art method.

摘要翻译： 步进机与在形成集成电路的过程中沉积材料层的硬件结合在一起，从而执行沉积，图案化和清洁，而不会将晶片暴露于工具之间的转移并结合复合工具中的三种工具的功能。 通过施加UV光通过步进器的掩模去除图案限定材料，从而消除现有技术方法的烘烤和显影步骤。 类似地，UV的泛滥暴露消除了现有技术方法的清洁步骤。

公开(公告)号：US20060035393A1

公开(公告)日：2006-02-16

申请号：US10710947

申请日：2004-08-13

申请人： Michael Chudzik ,  Joseph Shepard

发明人： Michael Chudzik ,  Joseph Shepard

IPC分类号： H01L21/66

CPC分类号： H01L21/02263 ,  C23C16/45525 ,  C23C16/52 ,  H01L21/0228 ,  H01L21/314

摘要： The invention provides methods for determining film continuity and growth modes in thin dielectric films. The continuity determining method comprises: depositing a material on the substrate using a first value of a growth metric; depositing an amount of charge on a surface of the material; repetitively measuring a surface voltage of the material until an onset of tunneling to provide a Vtunnel (or Etunnel) value; repeating the above steps for different values of the growth metric; and comparing the Vtunnel (or Etunnel) values for different values of the growth metric to provide a measure of the continuity of the material on the substrate. The growth modes of the material can be determined by comparing the first derivative of the Vtunnel or Etunnel per growth metric curve versus the growth metric, and examining the linearity of the results of the comparison.

摘要翻译： 本发明提供了确定薄介电膜中的膜连续性和生长模式的方法。 连续性确定方法包括：使用生长度量的第一值将材料沉积在衬底上; 在所述材料的表面上沉积一定量的电荷; 重复地测量材料的表面电压，直到隧道开始，以提供Vtunnel（或Etunnel）值; 对生长度量的不同值重复上述步骤; 以及比较生长度量值的不同值的Vtunnel（或Etunnel）值，以提供衬底上材料的连续性的量度。 材料的生长模式可以通过比较Vtunnel或Etunnel的每个生长度量曲线的一阶导数与生长指标，并检查比较结果的线性来确定。

公开(公告)号：US20050023664A1

公开(公告)日：2005-02-03

申请号：US10930304

申请日：2004-08-31

申请人： Michael Chudzik ,  Robert Dennard ,  Rama Divakaruni ,  Bruce Kenneth Furman ,  Rajarao Jammy ,  Chandrasekhar Narayan ,  Sampath Purushothaman ,  Joseph Shepard ,  Anna Wanda Topol

发明人： Michael Chudzik ,  Robert Dennard ,  Rama Divakaruni ,  Bruce Kenneth Furman ,  Rajarao Jammy ,  Chandrasekhar Narayan ,  Sampath Purushothaman ,  Joseph Shepard ,  Anna Wanda Topol

IPC分类号： H01L23/12 ,  H01L23/50 ,  H01L25/04 ,  H01L25/18 ,  H01L29/40 ,  H05K1/16 ,  H05K3/46 ,  H01L21/44 ,  H01L23/02 ,  H01L23/52

CPC分类号： H05K1/162 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/30105 ,  H05K1/167 ,  H05K3/4602 ,  H05K2201/09809

摘要： A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.

摘要翻译： 提供了一种用于半导体部件的载体，其具有集成在其基板中的无源部件。 无源组件包括去耦组件，例如电容器和电阻器。 一组连接被集成以提供与受支持的部件的紧密的电气接近。

公开(公告)号：US20070173008A1

公开(公告)日：2007-07-26

申请号：US11336727

申请日：2006-01-20

申请人： Michael Chudzik ,  Bruce Doris ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Yun Wang ,  Keith Wong

发明人： Michael Chudzik ,  Bruce Doris ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Yun Wang ,  Keith Wong

IPC分类号： H01L21/8238

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.

摘要翻译： 提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数 材料层与导电电极一起存在于电极堆叠中。 金属杂质的选择取决于电极是否具有n型功函数或p型功函数。 本发明还提供一种制造这种半导体结构的方法。 金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成 包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。

公开(公告)号：US07091118B1

公开(公告)日：2006-08-15

申请号：US10988532

申请日：2004-11-16

申请人： James Pan ,  John Pellerin ,  Linda R. Black ,  Michael Chudzik ,  Rajarao Jammy

发明人： James Pan ,  John Pellerin ,  Linda R. Black ,  Michael Chudzik ,  Rajarao Jammy

IPC分类号： H01L21/3205 ,  H01L21/338

CPC分类号： H01L29/7833 ,  H01L21/28052 ,  H01L29/66545 ,  H01L29/66583

摘要： A semiconductor device with a replacement metal gate and the process for making the same removes a dummy gate from a semiconductor device. Within the recess left by the dummy gate is a silicon layer on a gate dielectric layer. A replacement metal is deposited on the thin silicon layer and then reacted with the silicon layer to form a metal-rich silicon layer on the gate dielectric layer.

摘要翻译： 具有替换金属栅极的半导体器件及其制造方法从半导体器件中去除虚拟栅极。 在虚拟栅极留下的凹槽内是栅介质层上的硅层。 替代金属沉积在薄硅层上，然后与硅层反应，以在栅极介电层上形成富含金属的硅层。

公开(公告)号：US20080280404A1

公开(公告)日：2008-11-13

申请号：US11746759

申请日：2007-05-10

申请人： Michael Chudzik ,  Bruce B. Doris ,  William K. Henson ,  Hongwen Yan ,  Ying Zhang

发明人： Michael Chudzik ,  Bruce B. Doris ,  William K. Henson ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/311

CPC分类号： H01L29/045 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84

摘要： A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different NFET and pFET gate electrode materials.

摘要翻译： 形成微电子结构的方法使用位于目标层上的掩模层。 可以使用掩模层作为蚀刻掩模来蚀刻目标层，以从目标层形成端部锥形目标层。 可以在端部锥形目标层上形成另外的目标层，并用附加掩模层掩模。 可以蚀刻附加目标层以形成与端部锥形目标层分离的图案化附加目标层，并且不存在与端部锥形目标层相邻的附加靶层残余物。 该方法对于制造包括nFET和pFET栅电极的CMOS结构是有用的，其包括不同的NFET和pFET栅电极材料。

公开(公告)号：US20070161198A1

公开(公告)日：2007-07-12

申请号：US11306670

申请日：2006-01-06

申请人： Michael Chudzik ,  Paul Kirsch

发明人： Michael Chudzik ,  Paul Kirsch

IPC分类号： H01L21/336

CPC分类号： H01L29/66181 ,  H01L27/10867

摘要： A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of a portion of the doped deposition, deposition of an undoped insulator in the trench and removal of a portion of the doped and undoped insulators.

摘要翻译： 提供了一种沟槽器件及其制造方法。 沟槽装置具有带有第一部分的套环，该第一部分被掺杂，而第二部分是未掺杂的。 部分掺杂的环的制造可以通过在沟槽中沉积掺杂的绝缘体，去除掺杂沉积的一部分，在沟槽中沉积未掺杂的绝缘体以及去除掺杂和未掺杂的绝缘体的一部分来完成。

公开(公告)号：US07682917B2

公开(公告)日：2010-03-23

申请号：US12016326

申请日：2008-01-18

申请人： Stephen W. Bedell ,  Michael Chudzik ,  William K. Henson ,  Naim Moumen ,  Vijay Narayanan ,  Devendra K. Sadana ,  Kathryn T. Schonenberg ,  Ghavam Shahidi

发明人： Stephen W. Bedell ,  Michael Chudzik ,  William K. Henson ,  Naim Moumen ,  Vijay Narayanan ,  Devendra K. Sadana ,  Kathryn T. Schonenberg ,  Ghavam Shahidi

IPC分类号： H01L21/336

CPC分类号： H01L29/7847 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate spacer absorbs any oxygen during subsequent high temperature processing such as a stress memorization anneal. A metal is deposited over, and reacted with, the gate electrode and source and drain regions to form metal semiconductor alloy regions. The disposable gate spacer is subsequently removed selective to the metal semiconductor alloy regions. A porous or non-porous low-k dielectric material is deposited to provide a low parasitic capacitance between the gate electrode and the source and drain regions. The gate dielectric maintains the original dielectric constant since the disposable gate spacer prevents absorption of additional oxygen during high temperature processes.

摘要翻译： 一次性间隔物直接形成在栅极电极和栅极电介质的侧壁上或紧邻栅电极的侧壁上。 一次性间隔件包括清除氧的材料，例如金属，金属氮化物或具有高氧反应性的半导体材料。 一次性栅极间隔件在随后的高温处理例如应力记忆退火期间吸收任何氧气。 将金属沉积在栅电极和源极和漏极区上并与其反应以形成金属半导体合金区域。 一次性栅极间隔物随后被选择性地移除到金属半导体合金区域。 沉积多孔或非多孔低k电介质材料以在栅极电极和源极和漏极区域之间提供低的寄生电容。 栅极电介质保持原始介电常数，因为一次性栅极间隔物可防止在高温过程中吸收额外的氧。

公开(公告)号：US20060237803A1

公开(公告)日：2006-10-26

申请号：US10907935

申请日：2005-04-21

申请人： Wenjuan Zhu ,  Michael Chudzik ,  Oleg Gluschenkov ,  Dae-Gyu Park ,  Akihisa Sekiguchi

发明人： Wenjuan Zhu ,  Michael Chudzik ,  Oleg Gluschenkov ,  Dae-Gyu Park ,  Akihisa Sekiguchi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/28097 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

摘要： A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controlling stable material on top of a base gate dielectric layer, and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional metal atoms from their source through the diffusion-controlling material and into the base gate dielectric layer.

摘要翻译： 一种半导体结构及其制造方法，包括在基极电介质层的顶部形成扩散控制稳定材料的均匀缓冲层，然后形成含有过渡金属原子源的均匀层，然后退火 结构将过渡金属原子从其源极扩散通过扩散控制材料并进入基极栅极电介质层。