公开(公告)号：US06708288B1

公开(公告)日：2004-03-16

申请号：US09702590

申请日：2000-10-31

申请人： Michael L. Ziegler ,  Lawrence D. K. B. Dwyer ,  Carol L. Thompson

发明人： Michael L. Ziegler ,  Lawrence D. K. B. Dwyer ,  Carol L. Thompson

IPC分类号： G06F1100

CPC分类号： G06F11/1407 ,  G06F11/1469

摘要： Compiler-based checkpointing for error recovery. In various embodiments, a compiler is adapted to identify checkpoints in program code. Sets of data objects are associated with the checkpoints, and checkpoint code is generated by the compiler for execution at the checkpoints. The checkpoint code stores state information of the associated data objects for recovery if execution of the program is interrupted.

摘要翻译： 基于编译器的检查点进行错误恢复。 在各种实施例中，编译器适于识别程序代码中的检查点。 数据对象集合与检查点相关联，检查点代码由编译器生成，以便在检查点执行。 如果程序的执行中断，则检查点代码存储用于恢复的相关联的数据对象的状态信息。

公开(公告)号：US06845501B2

公开(公告)日：2005-01-18

申请号：US09917535

申请日：2001-07-27

申请人： Carol L. Thompson ,  Michael L. Zi gler ,  Jerome C. Huck ,  Lawrence D. K. B. Dwyer

发明人： Carol L. Thompson ,  Michael L. Zi gler ,  Jerome C. Huck ,  Lawrence D. K. B. Dwyer

IPC分类号： G06F9/38 ,  G06F9/45

CPC分类号： G06F9/383

摘要： A method for reducing cache memory misses in a computer that performs context switches between at least a first context and a second context. A First logic identifies a first prefetch region in a first memory element and a second logic identifies critical memory references within the first prefetch region during compilation of a computer program. The critical memory references within the first prefetch region correspond to data in cache memory if a context switch occurs from a process or thread associated with the second context to a process or thread associated with the first context during program execution. Third logic prefetches data associated with the identified critical memory references and stores the prefetched data in cache memory prior to a process or thread associated with the first context being resumed when a switch from the second context to the first context occurs during program execution.

摘要翻译： 一种用于减少在至少第一上下文和第二上下文之间进行上下文切换的计算机中的高速缓冲存储器缺失的方法。 A第一逻辑识别第一存储器元件中的第一预取区域，并且第二逻辑在汇编计算机程序期间识别第一预取区域内的关键存储器引用。 如果在程序执行期间如果从与第二上下文相关联的进程或线程发生到与第一上下文相关联的进程或线程的上下文切换，则第一预取区域内的关键内存引用对应于高速缓冲存储器中的数据。 第三逻辑预取与所识别的关键存储器引用相关联的数据，并且当在程序执行期间发生从第二上下文到第一上下文的切换时，在与第一上下文相关联的进程或线程之前，将预取数据存储在高速缓冲存储器中。

公开(公告)号：US06701518B1

公开(公告)日：2004-03-02

申请号：US09631552

申请日：2000-08-03

申请人： Lawrence D. K. B. Dwyer ,  Carol L. Thompson

发明人： Lawrence D. K. B. Dwyer ,  Carol L. Thompson

IPC分类号： G06F944

CPC分类号： G06F11/3624 ,  G06F8/52

摘要： The present invention relates to a system and method for reducing the adverse impact of assertion instructions to processor performance so that programmers will be encouraged to include assertion instructions in computer programs. The system of the present invention includes memory and a compiler. The memory stores a first program to be compiled by the compiler. The compiler, in compiling the first program, translates a first function of the first program into a second function of a second program. The first function has assertion instructions that are translated by the compiler into translated assertion instructions, which are included in the second function. In compiling the first program, the compiler enables selective execution, based on a run time input, of a portion of the translated assertion instructions included in the second function.

摘要翻译： 本发明涉及一种用于减少断言指令对处理器性能的不利影响的系统和方法，以便鼓励程序员在计算机程序中包括断言指令。 本发明的系统包括存储器和编译器。 内存存储由编译器编译的第一个程序。 编译器在编译第一程序时将第一程序的第一功能转换为第二程序的第二功能。 第一个函数具有由编译器转换成被转换为断言指令的断言指令，这些指令包含在第二个函数中。 在编译第一程序时，编译器使得能够基于运行时间输入来选择性地执行包括在第二功能中的翻译的断言指令的一部分。

公开(公告)号：US07191319B1

公开(公告)日：2007-03-13

申请号：US09631174

申请日：2000-08-02

申请人： Lawrence D. K. B. Dwyer ,  Michael L. Ziegler

发明人： Lawrence D. K. B. Dwyer ,  Michael L. Ziegler

IPC分类号： G06F9/312

CPC分类号： G06F9/3824 ,  G06F12/0862 ,  G06F2212/6024

摘要： In a multitasking computer system, data is preloaded into cache memory upon the occurrence of a context switch. To this end, processing circuitry stops executing a computer program during a first context switch in response to a first context switch command. Later, the processing circuitry resumes executing the computer program during a second context switch in response to a second context switch command. The memory control circuitry, in response to the second context switch command, identifies an address of computer memory that is storing a data value previously used to execute an instruction of the computer program prior to the first context switch. The memory control circuitry then retrieves the data value from the computer memory and stores the retrieved data value in the cache memory. Accordingly, the retrieved data value is available to the processing circuitry for use in executing instructions of the computer program after the second context switch without the processing circuitry having to request retrieval of the foregoing data value.

摘要翻译： 在多任务计算机系统中，在上下文切换发生时，将数据预加载到高速缓冲存储器中。 为此，响应于第一上下文切换命令，处理电路在第一上下文切换期间停止执行计算机程序。 之后，响应于第二上下文切换命令，处理电路在第二上下文切换期间恢复执行计算机程序。 响应于第二上下文切换命令，存储器控制电路识别正在存储先前用于在第一上下文切换之前执行计算机程序的指令的数据值的计算机存储器的地址。 存储器控制电路然后从计算机存储器检索数据值，并将所检索的数据值存储在高速缓冲存储器中。 因此，检索到的数据值可用于处理电路，用于在第二上下文切换之后执行计算机程序的指令，而无需处理电路必须请求检索前述数据值。

公开(公告)号：US07797505B2

公开(公告)日：2010-09-14

申请号：US11113461

申请日：2005-04-25

申请人： Edward J. Sharpe ,  Lawrence D. K. B. Dwyer ,  Steven M. Valentine ,  Eric W. Hamilton

发明人： Edward J. Sharpe ,  Lawrence D. K. B. Dwyer ,  Steven M. Valentine ,  Eric W. Hamilton

IPC分类号： G06F11/07

CPC分类号： G06F12/145 ,  G06F12/0223 ,  G06F12/1441

摘要： Systems, methods, and device are provided for program stack handling. One method embodiment includes recognizing that a fault has occurred because a particular address range in a memory stack has been accessed. The method includes evaluating a current utilized size of regions in the memory stack. A particular address range between the current utilized size of regions in the memory stack is then relocated.

摘要翻译： 提供系统，方法和设备用于程序堆栈处理。 一种方法实施例包括识别由于存储器堆栈中的特定地址范围已被访问而发生故障。 该方法包括评估当前利用的存储器堆栈中的区域的大小。 然后重新定位存储器堆栈中当前利用的区域大小之间的特定地址范围。

公开(公告)号：US07000151B2

公开(公告)日：2006-02-14

申请号：US10198776

申请日：2002-07-18

申请人： Lawrence D. K. B. Dwyer

发明人： Lawrence D. K. B. Dwyer

IPC分类号： G06F11/00

CPC分类号： G06F8/437 ,  G06F11/1004 ,  G06F11/3612

摘要： The present invention provides systems and methods for providing run-time type checking to prevent software errors. In architecture, a representative system includes a compiler that parses a program and further comprises a logic that generates a checksum for a block of code in the program, a logic that stores the checksum in the block of code, and a logic that inserts checksum instruction code into the block of code. The present invention can also be viewed as a method for providing run-time type checking to prevent software errors. A representative method operates by generating a checksum for a block of code in the program, and storing the checksum in the block of code. During execution of the program, a run-time checksum is generated for the block of code, and the block of code is executed if the checksum equals the run-time checksum, and the execution of the block of code is skipped if the checksum does not equals the run-time checksum.

摘要翻译： 本发明提供了用于提供运行时类型检查以防止软件错误的系统和方法。 在架构中，代表性系统包括解析程序的编译器，并且还包括为程序中的代码块生成校验和的逻辑，将代码块中的校验和存储的逻辑以及插入校验和指令的逻辑 代码进入代码块。 本发明还可以被视为提供运行时类型检查以防止软件错误的方法。 代表性的方法通过为程序中的代码块生成校验和来操作，并将校验和存储在代码块中。 在程序执行期间，为代码块生成运行时校验和，如果校验和等于运行时校验和，则执行代码块，如果校验和执行则跳过代码块的执行 不等于运行时校验和。

公开(公告)号：US06697971B1

公开(公告)日：2004-02-24

申请号：US09695363

申请日：2000-10-24

申请人： Lawrence D. K. B. Dwyer

发明人： Lawrence D. K. B. Dwyer

IPC分类号： H02H305

CPC分类号： G06F9/3824 ,  G06F9/3861 ,  G06F12/1441

摘要： A function of a computer program is executed by a computer system capable of detecting whether an instruction of the function, if executed, will access memory that has not been allocated to the function. More specifically, a memory device is loaded with data indicative of which locations of memory are allocated to a computer program function. Processing circuitry that is processing an instruction of the function for execution is configured to detect, based on the foregoing data, whether a memory location to be accessed via execution of the instruction is one of the memory locations allocated to the function. If the memory location is outside of the memory allocated to the function, the circuitry may prevent execution of the instruction and/or may transmit an error signal. Thus, data errors caused by accessing memory that has not been allocated to the function can be prevented.

摘要翻译： 计算机程序的功能由能够检测功能的指令（如果被执行）是否将访问尚未分配给该功能的存储器的计算机系统执行。 更具体地，存储器装置装载有指示存储器的哪个位置被分配给计算机程序功能的数据。 处理用于执行功能的指令的处理电路被配置为基于前述数据检测要通过指令的执行来访问的存储器位置是否是分配给该功能的存储器位置之一。 如果存储器位置在分配给功能的存储器之外，则电路可以阻止指令的执行和/或可以发送错误信号。 因此，可以防止由访问尚未分配给该功能的存储器引起的数据错误。