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    Software-controlled cache set management
    1.
    发明授权
    Software-controlled cache set management 失效
    软件控制缓存集管理

    公开(公告)号：US07120748B2

    公开(公告)日：2006-10-10

    申请号：US10655367

    申请日：2003-09-04

    申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Roy Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Roy Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

    IPC分类号： G06F12/00

    CPC分类号： G06F12/126

    摘要： The present invention provides a system for managing cache replacement eligibility. A first address register is configured to request an address from an L1 cache. An L1 cache is configured to determine whether a requested address is in the L1 cache and, in response to a determination that a requested address is not in the L1 cache, is further configured to transmit the requested address to a range register coupled to the L1 cache. The range register is configured to generate a class identifier in response to a received requested address and to transmit the requested address and class identifier to a replacement management table coupled to the range register. The replacement management table is configured to generate L2 tag replacement control indicia in response to a received requested address and class identifier. An L2 address register is coupled to the first address register and configured to request an address from an L2 cache. An L2 cache is coupled to the L2 address register and the replacement management table and is configured to determine whether a requested address is in the L2 cache and is further configured to assign replacement eligibility of at least one set of cache lines in the L2 cache in response to received L2 tag replacement control indicia. In response to a determination that a requested address is not in the L2 cache, the L2 cache is further configured to overwrite a cache line within a set of the L2 cache as a function of the replacement eligibility.

    摘要翻译： 本发明提供了一种用于管理高速缓存替换资格的系统。 第一地址寄存器被配置为从L1高速缓存请求地址。 L1缓存被配置为确定所请求的地址是否在L1高速缓存中，并且响应于所请求的地址不在L1高速缓存中的确定，还被配置为将所请求的地址发送到耦合到L1的范围寄存器 缓存。 范围寄存器被配置为响应于接收到的请求的地址生成类标识符，并将所请求的地址和类标识符发送到耦合到范围寄存器的替换管理表。 替换管理表被配置为响应于接收到的请求的地址和类标识符来生成L2标签替换控制标记。 L2地址寄存器耦合到第一地址寄存器并且被配置为从L2高速缓存请求地址。 L2缓存耦合到L2地址寄存器和替换管理表，并且被配置为确定所请求的地址是否在L2高速缓存中，并被进一步配置为在L2高速缓存中分配至少一组高速缓存行的替换资格 响应接收的L2标签替换控制标记。 响应于所请求的地址不在L2高速缓存中的确定，L2高速缓存进一步被配置为根据替换资格来覆盖L2高速缓存中的高速缓存行。

    On-chip data transfer in multi-processor system
    5.
    发明授权
    On-chip data transfer in multi-processor system 失效
    多处理器系统中的片上数据传输

    公开(公告)号：US06820143B2

    公开(公告)日：2004-11-16

    申请号：US10322127

    申请日：2002-12-17

    申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David Shippy ,  Thuong Quang Truong

    IPC分类号： G06F1328

    CPC分类号： G06F12/0817 ,  G06F12/0897

    摘要： A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

    摘要翻译： 提供了一种通过在不同处理器之间提供直接数据传输来提高计算机系统的性能的系统和方法。 该系统包括第一和第二处理器。 第一个处理器需要数据。 该系统还包括与第一处理器通信的目录。 目录接收到数据的数据请求，并包含有关数据存储位置的信息。 缓存耦合到第二处理器。 当发现数据被存储在高速缓存中时，内部总线耦合在第一处理器和高速缓存之间以将数据从高速缓存传送到第一处理器。

    Software-controlled cache set management
    7.
    发明申请
    Software-controlled cache set management 失效
    软件控制缓存集管理

    公开(公告)号：US20050055507A1

    公开(公告)日：2005-03-10

    申请号：US10655367

    申请日：2003-09-04

    申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

    发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

    IPC分类号： G06F12/00 ,  G06F12/12

    CPC分类号： G06F12/126

    摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

    摘要翻译： 本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。 根据地址未命中创建类标识符。 替换管理表可用于读取类标识符以创建标签替换控制标记。 包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

    Handling data cache misses out-of-order for asynchronous pipelines
    8.
    发明授权
    Handling data cache misses out-of-order for asynchronous pipelines 有权
    异步管道处理数据高速缓存无序乱序

    公开(公告)号：US07900024B2

    公开(公告)日：2011-03-01

    申请号：US12253448

    申请日：2008-10-17

    申请人： Christopher M. Abernathy ,  Jeffrey P. Bradford ,  Ronald P. Hall ,  Timothy H. Heil ,  David Shippy

    发明人： Christopher M. Abernathy ,  Jeffrey P. Bradford ,  Ronald P. Hall ,  Timothy H. Heil ,  David Shippy

    IPC分类号： G06F9/312

    CPC分类号： G06F9/30043 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3859 ,  G06F9/3861

    摘要： Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.

    摘要翻译： 提供了处理异步管道数据高速缓存未命中的机制。 这些机制将负载标签（LTAG）标识符与加载指令相关联，并使用它们来跟踪跨多个管道的加载指令作为加载目标缓冲区的加载表数据结构的索引。 加载表用于管理缓存“命中”和“未命中”，并帮助从L2缓存回收数据。 由于缓存未命中，LTAG索引的加载表允许加载数据以任何顺序从二级缓存中回收。 当加载指令发出并看到其在负载表中的相应条目标记为“未命中”时，发出加载指令的影响被取消，并且加载指令存储在加载表中，以便将来重新发布到指令流水线时 所需数据被回收。

    System and method for high frequency stall design
    9.
    发明授权
    System and method for high frequency stall design 失效
    高频失速设计系统及方法

    公开(公告)号：US07370176B2

    公开(公告)日：2008-05-06

    申请号：US11204414

    申请日：2005-08-16

    申请人： Jonathan James DeMent ,  Kurt Alan Feiste ,  Robert Alan Philhower ,  David Shippy

    发明人： Jonathan James DeMent ,  Kurt Alan Feiste ,  Robert Alan Philhower ,  David Shippy

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3875

    摘要： A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.

    摘要翻译： 提出了一种用于高频失速设计的系统和方法。 发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。 在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令 基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。 在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

    Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system
    10.
    发明申请
    Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system 审中-公开
    用于从包括主要问题队列阵列和辅助问题队列阵列在内的问题队列发出指令的方法和装置

    公开(公告)号：US20070198812A1

    公开(公告)日：2007-08-23

    申请号：US11236835

    申请日：2005-09-27

    申请人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

    发明人： Christopher Abernathy ,  Jonathan DeMent ,  Kurt Feiste ,  David Shippy

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857

    摘要： An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue includes a main array of storage cells and an auxiliary array of storage cells coupled thereto. When a particular row of the main array includes an instruction that is not ready-to-issue, a stall condition occurs for that instruction. However, to prevent the entire issue queue and processor from stalling, a ready-to-issue instruction in another row of the main array may bypass the row including the stalled or not-ready-to-issue instruction. To effect this bypass, the issue queue moves the ready-to-issue instruction to an issue row of the auxiliary array for issuance to an appropriate execution unit. Out-of-order issuance of instructions to the execution units thus continues despite the stalled instruction.

    摘要翻译： 信息处理系统包括处理器，其以程序顺序发出指令。 处理器包括一个问题队列，即使队列中的某些指令还没有准备就绪，也可能提前发出指令。 问题队列包括存储单元的主阵列和与其耦合的存储单元的辅助阵列。 当主阵列的特定行包含不能准备发出的指令时，该指令将发生停顿状态。 然而，为了防止整个问题队列和处理器停止，主阵列的另一行中的就绪指令可以绕过包括已停止或尚未准备就绪的指令的行。 为了实现此旁路，问题队列将准备就绪指令移动到辅助阵列的问题行以发布到适当的执行单元。 因此，执行单元的指令的乱序发布仍然停止。