公开(公告)号：US07691701B1

公开(公告)日：2010-04-06

申请号：US12348332

申请日：2009-01-05

申请人： Michael P. Belyansky ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Ravikumar Ramachandran ,  James Kenyon Schaeffer ,  Richard Wise ,  Keith Kwong Hon Wong ,  Hongwen Yan

发明人： Michael P. Belyansky ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Ravikumar Ramachandran ,  James Kenyon Schaeffer ,  Richard Wise ,  Keith Kwong Hon Wong ,  Hongwen Yan

IPC分类号： H01L21/00

CPC分类号： H01L21/823842 ,  H01L21/823857

摘要： Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated for first and second types of field-effect-transistors; forming a capping layer of a second TiN layer on top of the metal-containing layer; patterning the second TiN layer and the metal-containing layer to cover only a first portion of the first TiN layer, the first portion of the first TiN layer covering an area designated for the first type of field-effect-transistors; etching away a second portion of the first TiN layer exposed by the patterning while protecting the first portion of the first TiN layer, from the etching, through covering with at least a portion of thickness of the patterned metal-containing layer; and forming a third TiN layer covering an areas of the semiconductor substrate designated for the second type of field-effect-transistors.

摘要翻译： 本发明的实施例提供了一种形成场效应晶体管的栅叠层的方法。 该方法包括直接在第一氮化钛（TiN）层上形成含金属层，第一TiN层覆盖用于第一和第二类场效应晶体管的半导体衬底的区域; 在所述含金属层的顶部上形成第二TiN层的覆盖层; 图案化第二TiN层和含金属层以仅覆盖第一TiN层的第一部分，第一TiN层的第一部分覆盖指定用于第一类型的场效应晶体管的区域; 蚀刻通过图案化暴露的第一TiN层的第二部分，同时通过覆盖图案化的含金属层的厚度的至少一部分来保护第一TiN层的第一部分免受蚀刻; 以及形成覆盖指定用于第二类场效应晶体管的半导体衬底的区域的第三TiN层。

公开(公告)号：US20090152651A1

公开(公告)日：2009-06-18

申请号：US11958595

申请日：2007-12-18

申请人： Huiming Bu ,  Rick Carter ,  Michael P. Chudzik ,  Troy L. Graves ,  Michael A. Gribelyuk ,  Rashmi Jha ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Hongwen Yan ,  Bruce B. Doris ,  Keith Kwong Hon Wong

发明人： Huiming Bu ,  Rick Carter ,  Michael P. Chudzik ,  Troy L. Graves ,  Michael A. Gribelyuk ,  Rashmi Jha ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Hongwen Yan ,  Bruce B. Doris ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517

摘要： A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer.

摘要翻译： 晶体管在衬底中具有通道区域，在沟道区域的相对侧上具有衬底中的源极和漏极区域。 栅极堆叠形成在沟道区域上方的衬底上。 该栅极堆叠包括与衬底的沟道区域接触的界面层和与界面层（上）接触的高k电介质层（介电常数高于4.0）。 富氮的第一金属氮化物层在电介质层上接触，并且富金属的第二金属氮化物层与第一金属氮化物层接触（在）上。 最后，多晶硅帽与第二金属氮化物层接触（在）上。

公开(公告)号：US08901706B2

公开(公告)日：2014-12-02

申请号：US13345290

申请日：2012-01-06

申请人： Michael P. Chudzik ,  Bachir Dirahoui ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Oh-jung Kwon ,  Paul C. Parries ,  Hongwen Yan

发明人： Michael P. Chudzik ,  Bachir Dirahoui ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Oh-jung Kwon ,  Paul C. Parries ,  Hongwen Yan

IPC分类号： H01L21/02

CPC分类号： H01L28/91 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/84 ,  H01L27/10847 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/945

摘要： A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

摘要翻译： 在一个实施例中的沟槽结构包括存在于衬底中的沟槽，以及连续存在于沟槽的侧壁和基底上的电介质层。 电介质层的介电常数大于30.介电层由四方相铪氧化物组成，其中硅存在于四方相铪氧化物的晶界中，其量为3wt。 ％至20重量％ ％。

公开(公告)号：US20130175665A1

公开(公告)日：2013-07-11

申请号：US13345290

申请日：2012-01-06

申请人： Michael P. Chudzik ,  Bachir Dirahoui ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Oh-jung Kwon ,  Paul C. Parries ,  Hongwen Yan

发明人： Michael P. Chudzik ,  Bachir Dirahoui ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Oh-jung Kwon ,  Paul C. Parries ,  Hongwen Yan

IPC分类号： H01L29/92 ,  H01L21/02 ,  H01L29/06 ,  H01L21/31

CPC分类号： H01L28/91 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/84 ,  H01L27/10847 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/945

摘要： A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

公开(公告)号：US20100181630A1

公开(公告)日：2010-07-22

申请号：US12355953

申请日：2009-01-19

申请人： Huiming Bu ,  Michael P. Chudzik ,  Ricardo A. Donaton ,  Naim Moumen ,  Hongwen Yan

发明人： Huiming Bu ,  Michael P. Chudzik ,  Ricardo A. Donaton ,  Naim Moumen ,  Hongwen Yan

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4958 ,  H01L21/28079 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low resistance contact is formed to a metal gate or a transistor including a High-K gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.

摘要翻译： 通过在栅极堆叠上施加衬垫，在栅堆叠之间施加填充材料，将填充材料平坦化，将填充材料平坦化，形成低电阻接触到金属栅极或包括高集成度密度集成电路中的高K栅极电介质的晶体管 支持高分辨率光刻，相互选择性地蚀刻填充材料和衬垫以形成通孔并用金属，金属合金或导电金属化合物如氮化钛填充通孔。

公开(公告)号：US07863123B2

公开(公告)日：2011-01-04

申请号：US12355953

申请日：2009-01-19

申请人： Huiming Bu ,  Michael P. Chudzik ,  Ricardo A. Donaton ,  Naim Moumen ,  Hongwen Yan

发明人： Huiming Bu ,  Michael P. Chudzik ,  Ricardo A. Donaton ,  Naim Moumen ,  Hongwen Yan

IPC分类号： H01L21/336

CPC分类号： H01L29/4958 ,  H01L21/28079 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low resistance contact is formed to a metal gate or a transistor including a High-κ gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.

摘要翻译： 低电阻触点形成于金属栅极或包括高电平的晶体管。 通过在栅极堆叠上施加衬垫，在栅极叠层之间施加填充材料，平坦化填充材料以支持高分辨率光刻，相互选择性地蚀刻填充材料和衬垫，从而在高集成度密度集成电路中形成栅极电介质 形成通孔并用金属，金属合金或诸如氮化钛的导电金属化合物填充通孔。

公开(公告)号：US20090250760A1

公开(公告)日：2009-10-08

申请号：US12061081

申请日：2008-04-02

申请人： Michael P. Chudzik ,  William K. Henson ,  Naim Moumen ,  Dae-Gyu Park ,  Hongwen Yan

发明人： Michael P. Chudzik ,  William K. Henson ,  Naim Moumen ,  Dae-Gyu Park ,  Hongwen Yan

IPC分类号： H01L27/088 ,  H01L21/4763

CPC分类号： H01L21/84 ,  H01L21/823842 ,  H01L21/823857

摘要： Methods of forming high-k/metal gates for an NFET and PFET and a related structure are disclosed. One method includes recessing a PFET region; forming a first high-k dielectric layer and a first metal layer over the substrate; removing the first high-k dielectric layer and the first metal over the NFET region using a mask; forming a forming a second high-k dielectric layer and a second metal layer over the substrate, the first high-k dielectric layer being different then the second high-k dielectric layer and the first metal being different than the second metal; removing the second high-k dielectric layer and the second metal over the PFET region using a mask; depositing a polysilicon over the substrate; and forming a gate over the NFET region and the PFET region by simultaneously etching the polysilicon, the first high-k dielectric layer, the first metal, the second high-k dielectric layer and the second metal.

摘要翻译： 公开了形成用于NFET和PFET的高k /金属栅极和相关结构的方法。 一种方法包括使PFET区域凹陷; 在所述衬底上形成第一高k电介质层和第一金属层; 使用掩模在NFET区域上去除第一高k电介质层和第一金属; 在所述衬底上形成第二高k电介质层和第二金属层，所述第一高k电介质层与所述第二高k电介质层不同，所述第一金属与所述第二金属不同; 使用掩模在PFET区域上去除第二高k电介质层和第二金属; 在衬底上沉积多晶硅; 以及通过同时蚀刻多晶硅，第一高k电介质层，第一金属，第二高k电介质层和第二金属，在NFET区域和PFET区域上形成栅极。

公开(公告)号：US07081393B2

公开(公告)日：2006-07-25

申请号：US10709652

申请日：2004-05-20

申请人： Michael P. Belyansky ,  Joyce C. Liu ,  Hsing Jen Wann ,  Richard Stephen Wise ,  Hongwen Yan

发明人： Michael P. Belyansky ,  Joyce C. Liu ,  Hsing Jen Wann ,  Richard Stephen Wise ,  Hongwen Yan

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.

摘要翻译： FET晶体管具有设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 和在门侧的间隔物。 栅极电介质层是常规的氧化物，间隔物具有降低的介电常数（k）。 降低的介电常数（k）可以小于3.85，或者可以小于7.0（〜氮化物），但大于3.85（〜氧化物）。 优选地，间隔物包括可以选择性地蚀刻到栅极介电层的材料。 间隔物可以是多孔的，并且在多孔间隔物上沉积薄层以防止吸湿。 间隔物可以包括选自黑钻石，珊瑚，TERA和Blok型材料的材料。 可以通过将间隔物暴露于氧等离子体来在间隔物材料中形成孔。

公开(公告)号：US08193099B1

公开(公告)日：2012-06-05

申请号：US13049933

申请日：2011-03-17

申请人： Mukesh V. Khare ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Richard S. Wise ,  Hongwen Yan

发明人： Mukesh V. Khare ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Richard S. Wise ,  Hongwen Yan

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32136 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823828 ,  H01L21/823878

摘要： A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.

摘要翻译： 形成半导体器件的方法包括在具有有源区和浅沟槽隔离（STI）区的衬底上形成晶体管栅叠。 第一侧壁间隔物形成在晶体管栅极堆叠上，并且各向同性蚀刻工艺被应用于各向同性地去除包括在晶体管栅极叠层内的金属层的过剩部分，剩余部分未被第一侧壁间隔物保护。 第二侧壁间隔物形成在晶体管栅极叠层上，第二侧壁间隔物完全封装晶体管栅极叠层的金属层。

公开(公告)号：US06908806B2

公开(公告)日：2005-06-21

申请号：US10355726

申请日：2003-01-31

申请人： Haining Yang ,  Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Rajeev Malik ,  Hongwen Yan ,  Ravikumar Ramachandran

发明人： Haining Yang ,  Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Rajeev Malik ,  Hongwen Yan ,  Ravikumar Ramachandran

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/76838

摘要： A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.

摘要翻译： 一种制造半导体器件的方法，该半导体器件具有包括栅极叠层侧壁的栅极叠层结构，栅叠层结构具有一个或多个包含栅极金属的金属层。 栅极金属通过化学蚀刻从栅极堆叠侧壁凹入。 门堆叠结构的栅极金属被选择性地氧化以形成至少部分地填充凹部的金属氧化物。