公开(公告)号：US08575709B2

公开(公告)日：2013-11-05

申请号：US13556795

申请日：2012-07-24

申请人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

发明人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L21/2822 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66575

摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

摘要翻译： 用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。 在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。 在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。

公开(公告)号：US20100187610A1

公开(公告)日：2010-07-29

申请号：US12359520

申请日：2009-01-26

申请人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

发明人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.

摘要翻译： 半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层 第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且 第三金属层，第三金属层设置在第二中间层上。 或者，省略第一金属层。 制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

公开(公告)号：US20120286374A1

公开(公告)日：2012-11-15

申请号：US13556795

申请日：2012-07-24

申请人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

发明人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L21/2822 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66575

摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

摘要翻译： 用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。 在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。 在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。

公开(公告)号：US20110248350A1

公开(公告)日：2011-10-13

申请号：US12757323

申请日：2010-04-09

申请人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

发明人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L21/28176 ,  H01L21/28079 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/6659

摘要： Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

摘要翻译： 实现了包括包括Hi-K栅极电介质和金属栅极的栅极结构的场效应晶体管的开关阈值的调整，并且通过在与导电沟道相邻的薄界面层中提供固定的电荷材料来在NFET和PFET之间协调切换阈值 根据设计将Hi-K材料，优选氧化铪或HfSiON粘附到半导体材料上而不是将固定的电荷材料扩散到Hi-K材料中之后施加的晶体管。 固定电荷材料与晶体管的导通通道的接近程度增加了由于金属栅极的功函数而导致的固定电荷材料的调整阈值的有效性，特别是当相同的金属或合金用于NFET和PFET时 在集成电路中; 防止阈值正确协调。

公开(公告)号：US08728925B2

公开(公告)日：2014-05-20

申请号：US13463283

申请日：2012-05-03

申请人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

发明人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28176 ,  H01L21/28079 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/6659

摘要： Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

摘要翻译： 实现了包括包括Hi-K栅极电介质和金属栅极的栅极结构的场效应晶体管的开关阈值的调整，并且通过在与导电沟道相邻的薄界面层中提供固定的电荷材料来在NFET和PFET之间协调切换阈值 根据设计将Hi-K材料，优选氧化铪或HfSiON粘附到半导体材料上而不是将固定的电荷材料扩散到Hi-K材料中之后施加的晶体管。 固定电荷材料与晶体管的导通通道的接近程度增加了由于金属栅极的功函数而导致的固定电荷材料的调整阈值的有效性，特别是当相同的金属或合金用于NFET和PFET时 在集成电路中; 防止阈值正确协调。

公开(公告)号：US08318565B2

公开(公告)日：2012-11-27

申请号：US12721608

申请日：2010-03-11

申请人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

发明人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L21/2822 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66575

摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

摘要翻译： 用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。 在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。 在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。

公开(公告)号：US20120214299A1

公开(公告)日：2012-08-23

申请号：US13463283

申请日：2012-05-03

申请人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

发明人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

IPC分类号： H01L21/336

CPC分类号： H01L21/28176 ,  H01L21/28079 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/6659

摘要： Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

摘要翻译： 实现了包括包括Hi-K栅极电介质和金属栅极的栅极结构的场效应晶体管的开关阈值的调整，并且通过在与导电沟道相邻的薄界面层中提供固定的电荷材料来在NFET和PFET之间协调切换阈值 根据设计将Hi-K材料，优选氧化铪或HfSiON粘附到半导体材料上而不是将固定的电荷材料扩散到Hi-K材料中之后施加的晶体管。 固定电荷材料与晶体管的导通通道的接近程度增加了由于金属栅极的功函数而导致的固定电荷材料的调整阈值的有效性，特别是当相同的金属或合金用于NFET和PFET时 在集成电路中; 防止阈值正确协调。

公开(公告)号：US20110221012A1

公开(公告)日：2011-09-15

申请号：US12721608

申请日：2010-03-11

申请人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

发明人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L21/2822 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66575

摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

摘要翻译： 用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。 在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。 在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。

公开(公告)号：US08350341B2

公开(公告)日：2013-01-08

申请号：US12757323

申请日：2010-04-09

申请人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

发明人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

IPC分类号： H01L21/02

CPC分类号： H01L21/28176 ,  H01L21/28079 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/6659

摘要： Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

摘要翻译： 实现了包括包括Hi-K栅极电介质和金属栅极的栅极结构的场效应晶体管的开关阈值的调整，并且通过在与导电沟道相邻的薄界面层中提供固定的电荷材料来在NFET和PFET之间协调切换阈值 根据设计将Hi-K材料，优选氧化铪或HfSiON粘附到半导体材料上而不是将固定的电荷材料扩散到Hi-K材料中之后施加的晶体管。 固定电荷材料与晶体管的导通通道的接近程度增加了由于金属栅极的功函数而导致的固定电荷材料的调整阈值的有效性，特别是当相同的金属或合金用于NFET和PFET时 在集成电路中; 防止阈值正确协调。

公开(公告)号：US07838908B2

公开(公告)日：2010-11-23

申请号：US12359520

申请日：2009-01-26

申请人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

发明人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

IPC分类号： H01L27/10

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.

摘要翻译： 半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层 第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且 第三金属层，第三金属层设置在第二中间层上。 或者，省略第一金属层。 制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。