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    METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION
    4.
    发明申请
    METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION 有权
    金属氧化物半导体场效应晶体管（MOSFET）栅极终止

    公开(公告)号：US20130334618A1

    公开(公告)日：2013-12-19

    申请号：US13495081

    申请日：2012-06-13

    申请人： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

    发明人： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L21/28247 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/78

    摘要： A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

    摘要翻译： 提供一种形成半导体器件的方法，其包括在半导体衬底中形成含有隔离区的氧化物以限定有源半导体区域。 然后可以在有源半导体区域上形成包括高k栅极电介质层的覆盖栅极堆叠。 覆盖栅极堆叠的至少一部分从有源半导体器件区域延伸到隔离区域。 然后可以对覆盖栅极堆叠进行蚀刻以在隔离区域上提供开口。 然后可以对由开口暴露的隔离区域的表面进行各向同性蚀刻，以在隔离区域内形成在高k栅极电介质层下延伸的底切区域。 然后可以在填充底切区域的开口中形成密封电介质材料。 然后可以对覆盖栅极堆叠进行构图以形成栅极结构。

    Metal oxide semiconductor field effect transistor (MOSFET) gate termination
    6.
    发明授权
    Metal oxide semiconductor field effect transistor (MOSFET) gate termination 有权
    金属氧化物半导体场效应晶体管（MOSFET）门极端接

    公开(公告)号：US08704332B2

    公开(公告)日：2014-04-22

    申请号：US13495081

    申请日：2012-06-13

    申请人： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

    发明人： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

    IPC分类号： H01L29/786 ,  H01L29/78 ,  H01L29/06

    CPC分类号： H01L29/7816 ,  H01L21/28247 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/78

    摘要： A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

    摘要翻译： 提供一种形成半导体器件的方法，其包括在半导体衬底中形成含有隔离区的氧化物以限定有源半导体区域。 然后可以在有源半导体区域上形成包括高k栅极电介质层的覆盖栅极堆叠。 覆盖栅极堆叠的至少一部分从有源半导体器件区域延伸到隔离区域。 然后可以对覆盖栅极堆叠进行蚀刻以在隔离区域上提供开口。 然后可以对由开口暴露的隔离区域的表面进行各向同性蚀刻，以在隔离区域内形成在高k栅极电介质层下延伸的底切区域。 然后可以在填充底切区域的开口中形成密封电介质材料。 然后可以对覆盖栅极堆叠进行构图以形成栅极结构。

    STRESS ENGINEERING FOR SRAM STABILITY
    8.
    发明申请
    STRESS ENGINEERING FOR SRAM STABILITY 审中-公开
    用于SRAM稳定性的应力工程

    公开(公告)号：US20090166757A1

    公开(公告)日：2009-07-02

    申请号：US11964879

    申请日：2007-12-27

    申请人： Christopher V. Baiocco ,  Xiandong Chen ,  Young G. Ko ,  Melanie J. Sherony

    发明人： Christopher V. Baiocco ,  Xiandong Chen ,  Young G. Ko ,  Melanie J. Sherony

    IPC分类号： G06F17/50 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  G01R31/31816

    摘要： A design structure embodied in a machine readable medium is provided for use in the design, manufacturing, and/or testing of Ics that include at least one SRAM cell. In particular, the present invention provides a design structure of an IC embodied in a machine readable medium, the IC including at least one SRAM cell with a gamma ratio of about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC, there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides a design structure of an IC embodied in a machine readable medium, the IC comprising at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET.

    摘要翻译： 提供体现在机器可读介质中的设计结构用于设计，制造和/或测试包括至少一个SRAM单元的IC。 特别地，本发明提供了体现在机器可读介质中的IC的设计结构，该IC包括至少一个具有大约1或更大的伽马比的SRAM单元。 在本发明中，γ比随着pFET器件性能的降低而增加。 此外，在本发明的IC中，SRAM区域中不存在应力衬垫边界，与常规SRAM结构相比，所有器件的离子变化都降低。 本发明提供了体现在机器可读介质中的IC的设计结构，该IC包括至少一个包括至少一个nFET和至少一个pFET的静态随机存取存储器单元; 以及位于所述至少一个nFET和所述至少一个pFET之上并邻接所述至少一个nFET的连续松弛应力衬垫。

    DUAL LAYER STRESS LINER FOR MOSFETS
    9.
    发明申请
    DUAL LAYER STRESS LINER FOR MOSFETS 失效
    用于MOSFET的双层应力衬垫

    公开(公告)号：US20080153217A1

    公开(公告)日：2008-06-26

    申请号：US11616147

    申请日：2006-12-26

    申请人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    发明人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/31604 ,  H01L29/66575

    摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

    摘要翻译： 制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。 栅极结构和导体区域构成晶体管。 为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。 在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。 第二功率电平比第一功率电平高（例如，至少高5倍）。

    Method for transistor fabrication with optimized performance
    10.
    发明授权
    Method for transistor fabrication with optimized performance 有权
    具有优化性能的晶体管制造方法

    公开(公告)号：US07883953B2

    公开(公告)日：2011-02-08

    申请号：US12242078

    申请日：2008-09-30

    申请人： Da Zhang ,  Voon-Yew Thean ,  Christopher V. Baiocco ,  Jie Chen ,  Weipeng Li ,  Young Way Teh ,  Jin Wallner

    发明人： Da Zhang ,  Voon-Yew Thean ,  Christopher V. Baiocco ,  Jie Chen ,  Weipeng Li ,  Young Way Teh ,  Jin Wallner

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L29/045 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/7843

    摘要： A semiconductor process and apparatus includes forming channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).

    摘要翻译： 一种半导体工艺和设备包括在NMOS沟道区中形成具有增强的空穴迁移率的<100>沟道定向CMOS晶体管（24,34），并且通过在PMOS区上沉积第一拉伸蚀刻停止层（51），减小PMOS区域中的沟道缺陷率 蚀刻所述拉伸蚀刻停止层（51）以在所述暴露的栅极侧壁上形成拉伸侧壁间隔物（62），然后在所述NMOS和PMOS栅极上沉积第二富氢压缩或中性蚀刻停止层（72） 结构（26,36）和拉伸侧壁间隔物（62）。 在其它实施例中，沉积并蚀刻第一富氢蚀刻停止层（81）以在暴露的栅极侧壁上形成侧壁间隔物（92），然后在NMOS和PMOS上沉积第二拉伸蚀刻停止层（94） 栅极结构（26,36）和侧壁间隔物（92）。