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    LOW LEAKAGE ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
    2.
    发明申请
    LOW LEAKAGE ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT 失效
    低泄漏静电放电保护电路

    公开(公告)号：US20120120531A1

    公开(公告)日：2012-05-17

    申请号：US12943980

    申请日：2010-11-11

    申请人： Michel J. Abou-Khalil ,  Kiran V. Chatty ,  Robert J. Gauthier, JR.

    发明人： Michel J. Abou-Khalil ,  Kiran V. Chatty ,  Robert J. Gauthier, JR.

    IPC分类号： H02H9/00

    CPC分类号： H02H9/046

    摘要： A circuit and method for electrostatic discharge (ESD) protection. The ESD protection circuit includes: a silicon control rectifier (SCR) connected between a first voltage rail and a second voltage rail; one or more diodes connected in series in a forward conduction direction between the first voltage rail and a source of a p-channel field effect transistor (PFET); a drain of the PFET connected to the SCR and connected to ground through a current trigger device; and a control circuit connected to the gate of the PFET.

    摘要翻译： 一种用于静电放电（ESD）保护的电路和方法。 ESD保护电路包括：连接在第一电压轨和第二电压轨之间的硅控制整流器（SCR）; 在第一电压轨和p沟道场效应晶体管（PFET）的源极之间沿正向传导方向串联连接的一个或多个二极管; 连接到SCR的PFET的漏极通过电流触发装置连接到地; 以及连接到PFET的栅极的控制电路。

    Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure
    4.
    发明授权
    Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure 有权
    低泄漏，低电容静电放电（ESD）硅控制背光（SCR），制造方法和设计结构

    公开(公告)号：US08796731B2

    公开(公告)日：2014-08-05

    申请号：US12859801

    申请日：2010-08-20

    申请人： Michel J. Abou-Khalil ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

    发明人： Michel J. Abou-Khalil ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

    IPC分类号： H01L29/861

    CPC分类号： H01L29/7412 ,  H01L27/0262

    摘要： A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.

    摘要翻译： 提供了低泄漏，低电容二极管的触发静电放电（ESD）硅控整流器（SCR），制造方法和设计结构。 该方法包括在绝缘体层上提供硅膜。 该方法还包括形成从硅层的上侧延伸到绝缘体层的隔离区域。 该方法还包括在硅层中形成一个或多个二极管，包括形成在由隔离区界定的阱中的p +区和n +区。 隔离区域沿垂直方向隔离一个或多个二极管，并且绝缘体层在水平方向上将一个或多个二极管与下面的P或N型衬底隔离。

    Silicon controlled rectifier structure with improved junction breakdown and leakage control
    7.
    发明授权
    Silicon controlled rectifier structure with improved junction breakdown and leakage control 有权
    可控硅整流器结构，具有改进的结击穿和泄漏控制

    公开(公告)号：US08692290B2

    公开(公告)日：2014-04-08

    申请号：US13226838

    申请日：2011-09-07

    申请人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

    发明人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

    IPC分类号： H01L29/73 ,  H01L21/331 ,  G06F17/50

    CPC分类号： H01L29/66363 ,  G06F17/50 ,  H01L27/0262 ,  H01L29/74 ,  H01L29/7436 ,  H02H9/04

    摘要： Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.

    摘要翻译： 可控硅整流器的器件结构和设计结构，以及制造可控硅整流器的方法。 器件结构包括设置在包含可控硅整流器的第一和第二p-n结的器件区域的顶表面上的不同材料的第一和第二层。 第一层横向定位在与第一p-n结垂直对准的顶表面上。 第二层横向定位在与第二p-n结垂直对准的器件区域的顶表面上。 包括第二层的材料具有比包含第一层的材料更高的电阻率。

    Methods for forming back-end-of-line resistive semiconductor structures
    9.
    发明授权
    Methods for forming back-end-of-line resistive semiconductor structures 有权
    形成后端电阻半导体结构的方法

    公开(公告)号：US07977201B2

    公开(公告)日：2011-07-12

    申请号：US12191633

    申请日：2008-08-14

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/20

    CPC分类号： H01L23/5228 ,  H01L21/76816 ,  H01L23/5226 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.

    摘要翻译： 在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。 覆盖第一金属线的第二电介质层的一部分是使用光致抗蚀剂凹陷的，而第二金属线作为蚀刻掩模。 在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。 在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。 使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。 掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。

    Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory
    10.
    发明授权
    Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory 失效
    用于非易失性随机存取存储器的存储器单元的装置结构和用于非易失性随机存取存储器的设计结构

    公开(公告)号：US07804124B2

    公开(公告)日：2010-09-28

    申请号：US12118241

    申请日：2008-05-09

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42324

    摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.

    摘要翻译： 非易失性随机存取存储器（NVRAM）中存储单元的器件和设计结构。 器件结构包括与绝缘层直接接触的半导体本体，控制栅电极和与绝缘层直接接触的浮栅电极。 半导体本体包括源极，漏极以及源极和漏极之间的沟道。 浮置栅电极与半导体本体的沟道并置并且设置在控制栅电极和绝缘层之间。 第一电介质层设置在半导体本体的沟道和浮栅之间。 第二介电层设置在控制栅电极和浮栅电极之间。