公开(公告)号：US20080087949A1

公开(公告)日：2008-04-17

申请号：US11854183

申请日：2007-09-12

申请人： Michiaki MARUOKA ,  Kimimori HAMADA ,  Hidefumi TAKAYA

发明人： Michiaki MARUOKA ,  Kimimori HAMADA ,  Hidefumi TAKAYA

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734

摘要： A p-type epitaxial layer is formed on an n+-type substrate and then a buried n-type region is formed at a boundary between the n+-type substrate and the p-type epitaxial layer by ion implantation. Subsequently, a trench is formed so as to reach the n+-type substrate, passing through the p-type epitaxial layer and the buried n-type region. Then, a gate electrode is formed so as to deeply extend into the trench, i.e. to a position opposed to the buried n-type region. In a vertical MOSFET with this structure, when a positive voltage is applied to the gate electrode, an accumulation layer with a low resistance is formed in the buried n-type region, thereby reducing an on-resistance.

摘要翻译： 在n +型衬底上形成p型外延层，然后通过离子注入在n +型衬底和p型外延层之间的边界处形成掩埋的n型区域。 随后，形成沟槽，以便到达n +型衬底，穿过p型外延层和埋入的n型区域。 然后，形成栅电极，以便深深地延伸到沟槽中，即形成到与掩埋的n型区域相对的位置。 在具有这种结构的垂直MOSFET中，当向栅电极施加正电压时，在埋入的n型区域中形成具有低电阻的累积层，从而降低导通电阻。

公开(公告)号：US20170012122A1

公开(公告)日：2017-01-12

申请号：US15116288

申请日：2014-10-06

申请人： Hidefumi TAKAYA ,  Jun SAITO ,  Akitaka SOENO ,  Kimimori HAMADA ,  Shoji MIZUNO ,  Sachiko AOI ,  Yukihiko WATANABE

发明人： Hidefumi TAKAYA ,  Jun SAITO ,  Akitaka SOENO ,  Kimimori HAMADA ,  Shoji MIZUNO ,  Sachiko AOI ,  Yukihiko WATANABE

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7811 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.

摘要翻译： 半导体器件包括围绕其中设置有多个栅极沟槽的区域的端接沟槽; 与端子沟槽的下端接触的p型下端区域; p型外周区域，其从外周侧与所述端接沟槽接触并露出在所述半导体器件的表面上; 多个p型保护环区域，设置在p型外周区域的外周侧并露出在表面上; 以及将p型外周区域与保护环区域分离并将保护环区域彼此分离的n型外周区域。

公开(公告)号：US20140054688A1

公开(公告)日：2014-02-27

申请号：US14074212

申请日：2013-11-07

申请人： Hidefumi TAKAYA ,  Kimimori HAMADA ,  Yuji NISHIBE

发明人： Hidefumi TAKAYA ,  Kimimori HAMADA ,  Yuji NISHIBE

IPC分类号： H01L29/78

CPC分类号： H01L29/7815 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095

摘要： Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ∑ i = 1 n  ( R Mi × k Mi ) - ∑ i = 1 n  ( R Si × k Si ) ] / ∑ i = 1 n  ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.

摘要翻译： 提供了能够降低电流感测比的温度变化并精确检测电流的半导体器件。在半导体器件中，调整每个半导体层的杂质浓度和厚度中的至少一个，使得通过a 以下等式小于预定值：[Σi = 1 n（R Mi×k Mi） - Σi = 1 n（R Si×k Si）] /Σi = 1 n（R Mi×k Mi）其中主要元素域的第i个半导体层（i = 1至n）的温度依赖性电阻变化率为RMi; 主元件区域的第i个半导体层相对于整个主要元件区域的电阻比为kMi; 感测元件畴的第i个半导体层的温度依赖性电阻变化率为RSi; 并且感测元件畴的第i个半导体层与整个感测元件畴的电阻比为kSi。

公开(公告)号：US20140097490A1

公开(公告)日：2014-04-10

申请号：US14046361

申请日：2013-10-04

申请人： Hidefumi TAKAYA ,  Narumasa SOEJIMA

发明人： Hidefumi TAKAYA ,  Narumasa SOEJIMA

IPC分类号： H01L29/78

CPC分类号： H01L29/7831 ,  H01L29/0623 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted U-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted U-shaped section. The floating region protrudes under a portion that is located at a lowermost portion in the lower surface of the gate insulator.

摘要翻译： 半导体器件的半导体衬底包括第一导电类型的主体区域，与主体区域的下表面接触的第二导电类型的漂移区域，设置在通过所述主体区域的栅极沟槽中的栅电极 并且延伸到漂移区并面向身体区域，以及设置在栅极电极和栅极沟槽的壁表面之间的栅极绝缘体。 在栅极绝缘体的下表面形成倒U字状的截面，在倒U字状的截面形成有第一导电型的浮动区域。 浮动区域在位于栅极绝缘体的下表面中的最下部的部分下方突出。

公开(公告)号：US20110291110A1

公开(公告)日：2011-12-01

申请号：US13117575

申请日：2011-05-27

申请人： Naohiro SUZUKI ,  Hideo MATSUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Jun MORIMOTO ,  Tsuyoshi ISHIKAWA ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

发明人： Naohiro SUZUKI ,  Hideo MATSUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Jun MORIMOTO ,  Tsuyoshi ISHIKAWA ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

IPC分类号： H01L29/12 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.

摘要翻译： 碳化硅半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极绝缘层，栅极电极，源极电极，漏极电极和深层。 深层设置在基底区域下方并且位于比沟槽更深的深度。 深层在与沟槽的纵向方向交叉的方向上分成多个部分。 这些部分包括设置在与沟槽相对应的位置处的一组部分，其在沟槽的纵向方向上以相等的间隔布置。 该组部分围绕沟槽的底部的角落。

公开(公告)号：US20170084735A1

公开(公告)日：2017-03-23

申请号：US15365150

申请日：2016-11-30

申请人： Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Yuichi TAKEUCHI ,  Naohiro SUZUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L29/417 ,  H01L29/872 ,  H01L29/15 ,  H01L21/761

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

公开(公告)号：US20150129957A1

公开(公告)日：2015-05-14

申请号：US14505159

申请日：2014-10-02

申请人： Hidefumi TAKAYA ,  Katsuhiro KUTSUKI

发明人： Hidefumi TAKAYA ,  Katsuhiro KUTSUKI

IPC分类号： H01L29/78 ,  H01L27/088

CPC分类号： H01L29/7827 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7811 ,  H01L29/7813

摘要： A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches.

摘要翻译： 提供能够促进耗尽层的延伸并且几乎不引起热应力的沟槽结构。 半导体器件包括半导体衬底。 在半导体衬底的表面上形成多个环形沟槽。 每个环沟被配置为延伸以围绕小于形成多个栅极沟槽的区域的区域。 每个环形沟槽与其他环形沟槽分离。 第二绝缘层位于每个环沟中。 P型第四区域形成在半导体衬底中。 每个第四区域与对应的一个环形沟槽的底表面接触并且被配置为沿着相应的一个环形沟槽延伸。

公开(公告)号：US20120273801A1

公开(公告)日：2012-11-01

申请号：US13450639

申请日：2012-04-19

申请人： Hiroki WATANABE ,  Shinichiro MIYAHARA ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Yukihiko WATANABE ,  Narumasa SOEJIMA ,  Tsuyoshi ISHIKAWA

发明人： Hiroki WATANABE ,  Shinichiro MIYAHARA ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Yukihiko WATANABE ,  Narumasa SOEJIMA ,  Tsuyoshi ISHIKAWA

IPC分类号： H01L29/24

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7397

摘要： A SiC semiconductor device includes: a SiC substrate including a first or second conductive type layer and a first conductive type drift layer and including a principal surface having an offset direction; a trench disposed on the drift layer and having a longitudinal direction; and a gate electrode disposed in the trench via a gate insulation film. A sidewall of the trench provides a channel formation surface. The vertical semiconductor device flows current along with the channel formation surface of the trench according to a gate voltage applied to the gate electrode. The offset direction of the SiC substrate is perpendicular to the longitudinal direction of the trench.

摘要翻译： SiC半导体器件包括：SiC衬底，包括第一或第二导电类型层和第一导电类型漂移层，并且包括具有偏移方向的主表面; 设置在所述漂移层上并具有纵向方向的沟槽; 以及通过栅极绝缘膜设置在沟槽中的栅电极。 沟槽的侧壁提供通道形成表面。 垂直半导体器件根据施加到栅电极的栅极电压与沟道形成表面一起流动电流。 SiC衬底的偏移方向垂直于沟槽的纵向方向。

公开(公告)号：US20120161154A1

公开(公告)日：2012-06-28

申请号：US13330835

申请日：2011-12-20

申请人： Tomohiro MIMURA ,  Shinichiro MIYAHARA ,  Hidefumi TAKAYA ,  Masahiro SUGIMOTO ,  Narumasa SOEJIMA ,  Tsuyoshi ISHIKAWA ,  Yukihiko WATANABE

发明人： Tomohiro MIMURA ,  Shinichiro MIYAHARA ,  Hidefumi TAKAYA ,  Masahiro SUGIMOTO ,  Narumasa SOEJIMA ,  Tsuyoshi ISHIKAWA ,  Yukihiko WATANABE

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7397

摘要： An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region.

摘要翻译： SiC半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极氧化膜，栅电极，源电极和漏电极。 基板具有作为主表面的Si面。 源区具有Si面。 沟槽从源极区域的表面提供到比基部区域更深的部分并且在一个方向上纵向延伸并且具有Si面底部。 沟槽具有倒锥形形状，至少在与基部区域接触的部分处，入口部分处的宽度比底部宽。

公开(公告)号：US20120142173A1

公开(公告)日：2012-06-07

申请号：US13308721

申请日：2011-12-01

申请人： Hiroki WATANABE ,  Yasuo KITOU ,  Yasushi FURUKAWA ,  Kensaku YAMAMOTO ,  Hidefumi TAKAYA ,  Masahiro SUGIMOTO ,  Yukihiko WATANABE ,  Narumasa SOEJIMA ,  Tsuyoshi ISHIKAWA

发明人： Hiroki WATANABE ,  Yasuo KITOU ,  Yasushi FURUKAWA ,  Kensaku YAMAMOTO ,  Hidefumi TAKAYA ,  Masahiro SUGIMOTO ,  Yukihiko WATANABE ,  Narumasa SOEJIMA ,  Tsuyoshi ISHIKAWA

IPC分类号： H01L21/20 ,  C30B25/20 ,  C30B25/02

CPC分类号： H01L21/0262 ,  C30B25/186 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/046 ,  H01L21/0475 ,  H01L29/04

摘要： A manufacturing method of an SiC single crystal includes preparing an SiC substrate, implanting ions into a surface portion of the SiC substrate to form an ion implantation layer, activating the ions implanted into the surface portion of the SiC substrate by annealing, chemically etching the surface portion of the SiC substrate to form an etch pit that is caused by a threading screw dislocation included in the SiC substrate and performing an epitaxial growth of SiC to form an SiC growth layer on a surface of the SiC substrate including an inner wall of the etch pit in such a manner that portions of the SiC growth layer grown on the inner wall of the etch pit join with each other.

摘要翻译： SiC单晶的制造方法包括制备SiC衬底，将离子注入到SiC衬底的表面部分中以形成离子注入层，通过退火激活注入到SiC衬底的表面部分中的离子，化学蚀刻表面 以形成由SiC衬底中的螺纹位错引起的蚀刻坑，并且在SiC衬底的表面上进行SiC的外延生长以形成SiC生长层，所述SiC生长层包括蚀刻的内壁 以使得在蚀刻坑的内壁上生长的SiC生长层的部分彼此连接的方式形成凹坑。