公开(公告)号：US5933726A

公开(公告)日：1999-08-03

申请号：US709203

申请日：1996-08-27

申请人： Michio Nishimura ,  Kazuhiko Saitoh ,  Masayuki Yasuda ,  Takashi Hayakawa ,  Michio Tanaka ,  Yuji Ezaki ,  Katsuo Yuhara ,  Minoru Ohtsuka ,  Toshikazu Kumai ,  Songsu Cho ,  Toshiyuki Kaeriyama ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Jun Murata ,  Hideo Aoki ,  Akihiko Konno ,  Kiyomi Katsuyama ,  Takafumi Tokunaga ,  Yoshimi Torii

发明人： Michio Nishimura ,  Kazuhiko Saitoh ,  Masayuki Yasuda ,  Takashi Hayakawa ,  Michio Tanaka ,  Yuji Ezaki ,  Katsuo Yuhara ,  Minoru Ohtsuka ,  Toshikazu Kumai ,  Songsu Cho ,  Toshiyuki Kaeriyama ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Jun Murata ,  Hideo Aoki ,  Akihiko Konno ,  Kiyomi Katsuyama ,  Takafumi Tokunaga ,  Yoshimi Torii

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

摘要翻译： 诸如动​​态RAM的半导体器件及其制造方法。 在p型硅衬底（1）的顶部上沿着取向方向以规定的间隔放置多个堆叠的电池电容器。 每个电容器具有几乎垂直的圆柱形下电极（圆柱形多晶硅层（96）），电介质膜（氮化硅膜（77））和上电极（由多晶硅制成的板电极（78））。 排列方向上的间隔小于下电极的内径。

公开(公告)号：US5933724A

公开(公告)日：1999-08-03

申请号：US703067

申请日：1996-08-26

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Jun Murata ,  Katsuo Yuhara ,  Toshikazu Kumai ,  Michio Tanaka ,  Michio Nishimura ,  Kazuhiko Saitoh ,  Takatoshi Kakizaki ,  Takeshi Sakai ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Jun Murata ,  Katsuo Yuhara ,  Toshikazu Kumai ,  Michio Tanaka ,  Michio Nishimura ,  Kazuhiko Saitoh ,  Takatoshi Kakizaki ,  Takeshi Sakai ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： G03F1/28 ,  G03F1/30 ,  G03F1/36 ,  G03F1/68 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852

摘要： A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.

摘要翻译： 使用相移掩模来制造包括导体图案的半导体集成电路器件，其中图案化导体条的线宽或图案化导体条之间的空间不是恒定的。 对于对应于导体图案的掩模中的主要透明区域，提供辅助图案段以补偿由线宽或空间的变化引起的透射光的相位分布的变化。 或者，调节导体条之间的空间以抑制透射光的相分布的变化。 辅助图案片段是否应该具有相移功能是根据主透明区域的配置来确定的。

公开(公告)号：US06969649B2

公开(公告)日：2005-11-29

申请号：US10810884

申请日：2004-03-29

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Hideo Aoki ,  Toshikazu Kumai ,  Kazuhiko Saito ,  Michio Nishimura ,  Michio Tanaka ,  Katsuo Yuhara ,  Shinya Nishio ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Hideo Aoki ,  Toshikazu Kumai ,  Kazuhiko Saito ,  Michio Nishimura ,  Michio Tanaka ,  Katsuo Yuhara ,  Shinya Nishio ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： H01L21/8242 ,  H01L21/60 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

摘要翻译： 在一个实施例中，DRAM具有其上表面和侧表面被第一绝缘膜覆盖的多个字线，多个位线设置成与字线绝缘并横向于字线并被覆盖 具有第二绝缘膜和多个存储单元，每个存储单元设置在一个字线和一个位线之间的交点处，并且包括电容器和存储单元选择晶体管，其中用于在半导体区域和电容器之间以及半导体之间连接的接触孔 区域和位线形成为自对准，并且第二绝缘膜由电容率小于第一绝缘膜的介电常数的材料制成。

公开(公告)号：US06753219B2

公开(公告)日：2004-06-22

申请号：US10226290

申请日：2002-08-23

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Hideo Aoki ,  Toshikazu Kumai ,  Kazuhiko Saito ,  Michio Nishimura ,  Michio Tanaka ,  Katsuo Yuhara ,  Shinya Nishio ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Hideo Aoki ,  Toshikazu Kumai ,  Kazuhiko Saito ,  Michio Nishimura ,  Michio Tanaka ,  Katsuo Yuhara ,  Shinya Nishio ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： H01L218242

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

摘要翻译： 在一个实施例中，DRAM具有其上表面和侧表面被第一绝缘膜覆盖的多个字线，多个位线设置成与字线绝缘并横向于字线并被覆盖 具有第二绝缘膜和多个存储单元，每个存储单元设置在一个字线和一个位线之间的交点处，并且包括电容器和存储单元选择晶体管，其中用于在半导体区域和电容器之间以及半导体之间连接的接触孔 区域和位线形成为自对准，并且第二绝缘膜由电容率小于第一绝缘膜的介电常数的材料制成。

公开(公告)号：US20080214017A1

公开(公告)日：2008-09-04

申请号：US11967517

申请日：2007-12-31

申请人： Shigemi Murakawa ,  Toshikazu Kumai ,  Toshio Nakanishi

发明人： Shigemi Murakawa ,  Toshikazu Kumai ,  Toshio Nakanishi

IPC分类号： H01L21/31

CPC分类号： H01L21/28185 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02332 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/954 ,  Y10S438/981

摘要： A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

摘要翻译： MISFET（100）的栅极绝缘膜（104）由氧化硅膜（106），氮化硅膜（107）和高介电常数膜（108）构成。 氧化硅膜（106）和氮化硅膜（107）通过具有径向线槽天线的微波等离子体处理形成。

公开(公告)号：US07374635B2

公开(公告)日：2008-05-20

申请号：US11636695

申请日：2006-12-11

申请人： Shigemi Murakawa ,  Toshikazu Kumai ,  Toshio Nakanishi

发明人： Shigemi Murakawa ,  Toshikazu Kumai ,  Toshio Nakanishi

IPC分类号： C23F1/02

CPC分类号： H01L21/28185 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02332 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/954 ,  Y10S438/981

摘要： A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

摘要翻译： MISFET（100）的栅极绝缘膜（104）由氧化硅膜（106），氮化硅膜（107）和高介电常数膜（108）构成。 氧化硅膜（106）和氮化硅膜（107）通过具有径向线槽天线的微波等离子体处理形成。

公开(公告)号：US06852194B2

公开(公告)日：2005-02-08

申请号：US10147990

申请日：2002-05-20

申请人： Minoru Matsushita ,  Yasushi Kodashima ,  Toshikazu Kumai

发明人： Minoru Matsushita ,  Yasushi Kodashima ,  Toshikazu Kumai

IPC分类号： C23C16/54 ,  H01L21/00 ,  H01L21/677 ,  C23F1/00 ,  C23C16/00

CPC分类号： H01L21/67745 ,  C23C16/54 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67742 ,  Y10S414/139

摘要： Processing apparatus is disclosed, that comprises substrate container holding table that can hold substrate container that contains plurality of target substrates, first transferring chamber, disposed adjacent to the substrate container holding table, that maintains the interior at first pressure, first processing unit group, disposed around the first transferring chamber, that processes target substrate at the first pressure, first transferring mechanism, disposed in the first transferring chamber, that transfers target substrate, second transferring chamber, disposed adjacent to the first transferring chamber, that maintains the interior at second pressure, second processing unit group, disposed around the second transferring chamber, that processes target substrate at the second pressure, and second transferring mechanism, disposed in the second transferring chamber, wherein the first transferring mechanism and/or the second transferring mechanism has at least two transferring arms.

摘要翻译： 公开了一种处理装置，其包括可容纳多个目标基板的基板容器的基板容器保持台，第一处理单元组，第一处理单元组，设置在基板容器保持台附近设置的第一传送室 围绕第一传送室，处理设置在第一传送室中的第一压力下的目标基板，第一传送机构，传送目标基板，邻近第一传送室设置的第二传送室，其将内部维持在第二压力 第二处理单元组，设置在第二转印室周围，处理第二压力下的目标基板;以及第二转印机构，设置在第二转印室中，其中第一转印机构和/或第二转印机构具有至少两个 转移武器

公开(公告)号：US20070085154A1

公开(公告)日：2007-04-19

申请号：US11636695

申请日：2006-12-11

申请人： Shigemi Murakawa ,  Toshikazu Kumai ,  Toshio Nakanishi

发明人： Shigemi Murakawa ,  Toshikazu Kumai ,  Toshio Nakanishi

IPC分类号： H01L21/8238

CPC分类号： H01L21/28185 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02332 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/954 ,  Y10S438/981

摘要： A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

摘要翻译： MISFET（100）的栅极绝缘膜（104）由氧化硅膜（106），氮化硅膜（107）和高介电常数膜（108）构成。 氧化硅膜（106）和氮化硅膜（107）通过具有径向线槽天线的微波等离子体处理形成。

公开(公告)号：US07166185B2

公开(公告)日：2007-01-23

申请号：US10487986

申请日：2002-08-29

申请人： Shigemi Murakawa ,  Toshikazu Kumai ,  Toshio Nakanishi

发明人： Shigemi Murakawa ,  Toshikazu Kumai ,  Toshio Nakanishi

IPC分类号： C23F1/02 ,  C23C16/00

CPC分类号： H01L21/28185 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02332 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/954 ,  Y10S438/981

摘要： The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

摘要翻译： 氧化硅膜（106）和氮化硅膜（107）通过具有径向线槽天线的微波等离子体处理形成。