公开(公告)号：US12293783B2

公开(公告)日：2025-05-06

申请号：US17829054

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Giovanni Mazzeo

IPC: G11C11/22

Abstract: Systems and methods related to a memory device that includes a command interface configured to receive read commands and write commands to invoke read and write operations. The memory device also includes a memory bank having multiple memory cells implemented using ferroelectric layers between plate lines and digit lines. The memory device also includes bank control circuitry configured to control operation of the memory bank. The operation of the memory bank includes programming both high and low logic values as a write back to the multiple memory cells during a read and write phase where the read and write operations are performed after sensing values from the multiple memory cells.

公开(公告)号：US12255984B2

公开(公告)日：2025-03-18

申请号：US17331578

申请日：2021-05-26

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Simon J. Lovett

IPC: H04L9/06 ,  G06F3/06 ,  G06F21/62 ,  G11C29/38 ,  G11C29/44 ,  G06F7/58 ,  H04L9/08

Abstract: Methods, systems, and devices for memory operations are described. First scrambling sequences may be generated for first addresses of a memory device after an occurrence of a first event, where the first addresses may be associated with commands received at the memory device. Portions of the memory array corresponding to the first address may be accessed based on the first scrambling sequences. After an occurrence of a subsequent event, second scrambling sequences may be generated for the first addresses, where the second scrambling sequences may be different than the first set of scrambling sequences. After the occurrence of the subsequent event, the portions of the memory array may be accessed based on the second scrambling sequences.

公开(公告)号：US12142311B2

公开(公告)日：2024-11-12

申请号：US17829046

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Tong Liu ,  Daniele Vimercati

IPC: G11C11/22

Abstract: Systems and methods are related to a memory device including a plate line. The memory device also includes a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line. The memory device further includes a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers. The memory device also includes a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the digit lines from the respective memory cells. The sense amplifier includes a threshold voltage compensated latch that includes multiple p-channel transistors and is configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the multiple p-channel transistors.

公开(公告)号：US12027192B2

公开(公告)日：2024-07-02

申请号：US17470655

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.

公开(公告)号：US11917809B2

公开(公告)日：2024-02-27

申请号：US17863970

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C7/10 ,  H10B12/00 ,  H01L27/06 ,  G11C11/408 ,  G11C11/22 ,  H01L29/786 ,  H10B53/20

CPC classification number: H10B12/30 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/408 ,  H01L27/0688 ,  H01L29/78642 ,  H10B53/20

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

公开(公告)号：US20240055056A1

公开(公告)日：2024-02-15

申请号：US17888298

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C16/26 ,  G11C13/00 ,  G11C16/12 ,  G11C11/22

CPC classification number: G11C16/26 ,  G11C13/004 ,  G11C16/12 ,  G11C13/003 ,  G11C11/2259

Abstract: Methods, systems, and devices for storing bits, such as N−1 bits, with cells, such as N cells, in a memory device are described. A memory device may generate a first sensing voltage that is based on a first voltage of a first digit line and a second voltage of a second digit line. The memory device may also generate a second sensing voltage that is based on a third voltage of a third digit line and a fourth voltage of a fourth digit line. The memory device may then determine a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.

公开(公告)号：US20230410871A1

公开(公告)日：2023-12-21

申请号：US17829054

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Giovanni Mazzeo

IPC: G11C11/22

CPC classification number: G11C11/2293 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/221

Abstract: Systems and methods related to a memory device that includes a command interface configured to receive read commands and write commands to invoke read and write operations. The memory device also includes a memory bank having multiple memory cells implemented using ferroelectric layers between plate lines and digit lines. The memory device also includes bank control circuitry configured to control operation of the memory bank. The operation of the memory bank includes programming both high and low logic values as a write back to the multiple memory cells during a read and write phase where the read and write operations are performed after sensing values from the multiple memory cells.

公开(公告)号：US11763871B2

公开(公告)日：2023-09-19

申请号：US17582941

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2293 ,  G11C11/2297

Abstract: Memory cells are described that include two reference voltages that may store and sense three distinct memory states by compensating for undesired intrinsic charges affecting a memory cell. Although embodiments described herein refer to three memory states, it should be appreciated that in other embodiments, the memory cell may store or sense more than three charge distributions using the described methods and techniques. In a first memory state, a programming voltage or a sensed voltage may be higher than a first reference voltage and a second reference voltage. In a second memory state, the applied voltage or the sensed voltage may be between the first and the second reference voltages. In a third memory state, the applied voltage or the sensed voltage may be lower than the first and the second reference voltages. As such, the memory cell may store and retrieve three memory states.

公开(公告)号：US11763870B2

公开(公告)日：2023-09-19

申请号：US17661348

申请日：2022-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  H10B53/20 ,  H10B53/30

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2275 ,  H10B53/20 ,  H10B53/30

Abstract: Apparatuses, systems, and methods for ferroelectric memory (FeRAM) cell operation. An FeRAM cell may have different charge regions it can operate across. Some regions, such as dielectric regions, may operate faster, but with reduced signal on a coupled digit line. To improve the performance while maintaining increased speed, two digit lines may be coupled to the same sense amplifier, so that the FeRAM cells coupled to both digit lines contribute signal to the sense amplifier. For example a first digit line in a first deck of the memory and a second digit line in a second deck of the memory may both be coupled to the sense amplifier. In some embodiments, additional digit lines may be used as shields (e.g., by coupling the shield digit lines to a ground voltage) to further improve the signal-to-noise ratio.

公开(公告)号：US11751386B2

公开(公告)日：2023-09-05

申请号：US17399315

申请日：2021-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Vimercati

IPC: G11C16/06 ,  H10B41/27 ,  G11C5/02 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C16/06 ,  H10B43/27

Abstract: Field-effect transistors, and integrated circuit devices containing such field-effect transistors, might include a semiconductor material having a first conductivity type, a first source/drain region having a second conductivity type, a second source/drain region having the second conductivity type, a first contact connected to the first source/drain region, a conductor overlying an active area of the semiconductor material and having an annular portion surrounding the first contact and a spur portion extending from an outer perimeter of the annular portion of the conductor, a second contact connected to the second source/drain region outside the annular portion of the conductor, a dielectric between the conductor and the active area, and a third contact overlying the active area and connected to the spur portion of the conductor.