公开(公告)号：US20240094942A1

公开(公告)日：2024-03-21

申请号：US18521789

申请日：2023-11-28

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A request to perform a data operation associated with at least one memory unit in a plurality of memory units of a memory device is received. The at least one memory unit includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having the specified charge level represents a non-integer number of bits. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The data operation is performed with respect to the at least one memory unit based on a mapping stored on the system. The mapping assigns an individual sequence of charge levels from an individual group cell to an individual sequence of bits represented by the individual group of memory cells.

公开(公告)号：US11568937B2

公开(公告)日：2023-01-31

申请号：US17216015

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen ,  Phong Sy Nguyen

IPC: G11C16/10 ,  G11C16/26 ,  G11C7/10 ,  G11C16/30

Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.

公开(公告)号：US11562776B2

公开(公告)日：2023-01-24

申请号：US17342171

申请日：2021-06-08

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen

IPC: G11C7/00 ,  G11C7/10 ,  H03K19/20 ,  H03K23/00

Abstract: A request to perform a read operation on a memory device is received. The memory device includes a first group of memory cells. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The read operation is performed by obtaining a first read signal for a first memory cell and a second read signal for a second memory cell of the first group of memory cells. A first rule logic is applied to the first read signal to generate a first updated signal and a second rule logic is applied to the second read signal to generate a second updated signal. Logic functions are applied to the first and second updated signals to generate an output signal indicating the first sequence of bits stored by the first group of memory cells.

公开(公告)号：US20240231617A1

公开(公告)日：2024-07-11

申请号：US18612028

申请日：2024-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

公开(公告)号：US11869595B2

公开(公告)日：2024-01-09

申请号：US18085228

申请日：2022-12-20

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen ,  Phong Sy Nguyen

IPC: G11C16/10 ,  G11C16/26 ,  G11C7/10 ,  G11C16/30

CPC classification number: G11C16/10 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/26 ,  G11C16/30

Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.

公开(公告)号：US20220310164A1

公开(公告)日：2022-09-29

申请号：US17216015

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen ,  Phong Sy Nguyen

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C7/10

Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.

公开(公告)号：US12131060B2

公开(公告)日：2024-10-29

申请号：US17872426

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Dung V. Nguyen ,  Dave Scott Ebsen ,  Tomoharu Tanaka ,  James Fitzpatrick ,  Huai-Yuan Tseng ,  Akira Goda ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

公开(公告)号：US11861208B2

公开(公告)日：2024-01-02

申请号：US17131319

申请日：2020-12-22

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A request to perform a data operation associated with at least one memory unit in a plurality of memory units of a memory device is received. The at least one memory unit includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having the specified charge level represents a non-integer number of bits. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The data operation is performed with respect to the at least one memory unit based on a mapping stored on the system. The mapping assigns an individual sequence of charge levels from an individual group cell to an individual sequence of bits represented by the individual group of memory cells.

公开(公告)号：US20220197538A1

公开(公告)日：2022-06-23

申请号：US17131319

申请日：2020-12-22

Applicant: Micron Technology, Inc,

Inventor： Dung V. Nguyen

IPC: G06F3/06

Abstract: A request to perform a data operation associated with at least one memory unit in a plurality of memory units of a memory device is received. The at least one memory unit includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having the specified charge level represents a non-integer number of bits. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The data operation is performed with respect to the at least one memory unit based on a mapping stored on the system. The mapping assigns an individual sequence of charge levels from an individual group cell to an individual sequence of bits represented by the individual group of memory cells.

公开(公告)号：US20250013382A1

公开(公告)日：2025-01-09

申请号：US18895273

申请日：2024-09-24

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Dung V. Nguyen ,  Dave Scott Ebsen ,  Tomoharu Tanaka ,  James Fitzpatrick ,  Huai-Yuan Tseng ,  Akira Goda ,  Eric N. Lee

IPC: G06F3/06

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.