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1.发明公开公开(公告)号：US20240349478A1
公开(公告)日：2024-10-17
申请号：US18619000
申请日：2024-03-27
IPC分类号： H10B12/00
CPC分类号： H10B12/0335 , H10B12/315 , H10B12/482 , H10B12/485
摘要： A method of forming a microelectronic device includes forming a first dielectric stack over a semiconductor base structure including pillar structures separated by filled isolation trenches. Digit line contacts are formed to partially vertically extend through the first dielectric stack and into digit line contact regions of the pillar structures. Digit lines are formed over and in contact with the digit line contacts, and partially vertically extend through the first dielectric stack. A second dielectric stack is formed over the digit lines and the first dielectric stack. Storage node contacts are formed to vertically extend partially through the second dielectric stack, completely through the first dielectric stack, and into storage node contact regions of the pillar structures. Redistribution layer structures are formed over and in contact with the storage node contacts, and partially vertically extend through the second dielectric stack. Microelectronic devices, memory devices, and electronic systems are also described.
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公开(公告)号：US11930643B2
公开(公告)日：2024-03-12
申请号：US17327031
申请日：2021-05-21
摘要： Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.
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公开(公告)号：US20240074142A1
公开(公告)日：2024-02-29
申请号：US17898233
申请日：2022-08-29
IPC分类号： H01L27/108
CPC分类号： H01L27/10805 , H01L27/10885
摘要： A microelectronic device comprises a vertical stack of memory cells. Each vertical stack of memory cells comprises a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure in electrical communication with the vertical stack of access devices. The microelectronic device further comprises first global digit lines vertically neighboring the vertical stacks of memory cells, and second global digit lines horizontally interleaved with the first global digit lines in a horizontal direction, the second global digit lines vertically spaced from the vertical stacks of memory cells a greater distance than the first global digit lines. Related memory devices, electronic systems, and methods are also described.
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4.发明公开公开(公告)号：US20230397398A1
公开(公告)日：2023-12-07
申请号：US17805201
申请日：2022-06-02
IPC分类号： H01L27/108
CPC分类号： H01L27/10805 , H01L27/10897 , H01L27/1085 , H01L27/10873
摘要： A microelectronic device comprises vertical stacks of memory cells, each vertical stack of memory cells comprising a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure vertically extending through the vertical stack of access devices. The microelectronic device further comprises multiplexers and additional transistors vertically overlying the vertical stacks of memory cells, and global digit lines vertically overlying the multiplexer and the additional transistor. Related electronic systems and methods are also described.
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公开(公告)号：US11810901B2
公开(公告)日：2023-11-07
申请号：US17344444
申请日：2021-06-10
发明人： Fatma Arzum Simsek-Ege , Yuan He
CPC分类号： H01L25/0657 , H01L25/18 , H01L25/50 , H01L24/32 , H01L27/1207 , H01L2224/32145 , H01L2924/1431 , H01L2924/1436 , H10B12/50
摘要： A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.
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公开(公告)号：US11690216B2
公开(公告)日：2023-06-27
申请号：US16713913
申请日：2019-12-13
IPC分类号： H01L21/768 , H01L23/522 , H01L23/00 , H01L23/31 , H01L23/495 , H01L23/528 , H01L23/532 , H10B12/00
CPC分类号： H10B12/34 , H10B12/053 , H10B12/488 , H10B12/31
摘要： An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by the channel. The example apparatus further includes a gate separated from the channel by a dielectric material and an access line formed in a high aspect ratio trench connected to the gate. The access line includes a first titanium nitride (TiN) material formed in the trench, a metal material formed over the first TiN material, and a second TiN material formed over the metal material. The example apparatus further includes a sense line coupled to the first source/drain region and a storage node coupled to the second source/drain region.
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7.发明申请公开(公告)号：US20230067220A1
公开(公告)日：2023-03-02
申请号：US17461095
申请日：2021-08-30
发明人： Fatma Arzum Simsek-Ege , Yuan He
IPC分类号： H01L27/108 , G11C5/10 , G11C11/407 , G11C5/02
摘要： A microelectronic device comprises array regions individually comprising memory cells comprising access devices and storage node device, digit lines coupled to the access devices and extending in a first direction, word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises capacitor regions horizontally offset from the array regions in the first direction and having a dimension in the second direction greater than each individual array region in the second direction. The capacitor regions individually comprise additional control logic devices vertically overlying the memory cells, and capacitor structures within horizontal boundaries of the additional control logic devices. Related microelectronic devices, electronic systems, and methods are also described.
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公开(公告)号：US20230005932A1
公开(公告)日：2023-01-05
申请号：US17364281
申请日：2021-06-30
IPC分类号： H01L27/108
摘要： A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.
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9.发明申请公开(公告)号：US20220399309A1
公开(公告)日：2022-12-15
申请号：US17344519
申请日：2021-06-10
IPC分类号： H01L25/065 , H01L23/528 , H01L23/532 , H01L23/00 , H01L25/00
摘要： A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a memory array region comprising a stack structure comprising levels of conductive structures vertically alternating with levels of insulative structures, and staircase structures at lateral ends of the stack structure. The memory array region further comprises vertical stacks of memory cells, at least one of the vertical stacks of memory cells comprising stacked capacitor structures, each stacked capacitor structure comprising capacitor structures vertically spaced from each other by at least a level of the levels of insulative structures, transistor structures, each transistor structure operably coupled to a capacitor structure and to one of the conductive structures of the levels of conductive structures, and a conductive pillar structure vertically extending through the transistor structures. The first microelectronic device further comprises conductive contact structures in electrical communication with the levels of conductive structures at steps of the staircase structures. The second microelectronic device comprises control logic devices configured to effectuate at least a portion of control operations for the vertical stacks of memory cells, conductive interconnect structures vertically extending through an oxide material and in electrical communication with the conductive contact structures, and an additional conductive interconnect structure vertically extending through the oxide material and in electrical communication with the conductive pillar structure of the at least one of the vertical stacks of memory cells. Related microelectronic devices, electronic systems, and methods are also described.
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公开(公告)号：US20220342386A1
公开(公告)日：2022-10-27
申请号：US17861374
申请日：2022-07-11
发明人： Fatma Arzum Simsek-Ege , Shruthi Kumara Vadivel , Deepti Verma , Anshika Sharma , Lavanya Sriram , Trupti D. Gawai
IPC分类号： G05B19/4093 , G05B19/418
摘要： Methods, devices, and systems related to process control in manufacturing are described. In an example, a method can include receiving data from a first process control device affixed to a first manufacturing tool of a first type, identifying one or more attributes of the data via a second processing resource of a second process control device affixed to a second manufacturing tool of a second type different from the first type, determining one or more settings for the second manufacturing tool via the second processing resource in response to identifying the one or more attributes of the data, and sending a command including the one or more settings to the second manufacturing tool from the second process control device.
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